-
公开(公告)号：US10811068B2
公开(公告)日：2020-10-20
申请号：US16247247
申请日：2019-01-14
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Wei-Chuan Chen , Wah Nam Hsu , Seung Hyuk Kang
Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
-
公开(公告)号：US20190051341A1
公开(公告)日：2019-02-14
申请号：US15676957
申请日：2017-08-14
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Wah Nam Hsu , Wei-Chuan Chen , Seung Hyuk Kang
IPC: G11C11/16
Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.
-
公开(公告)号：US10060880B2
公开(公告)日：2018-08-28
申请号：US15266342
申请日：2016-09-15
Applicant: QUALCOMM Incorporated
Inventor： Wei-Chuan Chen , Jung Pill Kim , Seung Hyuk Kang
CPC classification number: G01N27/745 , B82Y25/00 , G01R33/09 , G01R33/093 , G01R33/098
Abstract: Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing are provided. These MR sensors may be used as biosensors to detect the presence of biological materials as an example. An MR sensor includes dual MR sensor devices that may be tunnel magnetoresistive (TMR) devices or giant magnetoresistive (GMR) devices as examples. The MR devices are arranged such that a channel is formed between the MR devices for receiving magnetic nanoparticles. A magnetic stray field generated by the magnetic nanoparticles causes free layers in the MR devices to rotate in opposite directions, thus causing differential resistances between the MR devices for greater sensing sensitivity. Further, as another aspect, by providing the channel between the MR devices, the magnetic stray field generated by the magnetic nanoparticles can more easily rotate the magnetic moment orientation of the free layers in the MR devices, thus further increasing sensitivity.
-
公开(公告)号：US09666792B2
公开(公告)日：2017-05-30
申请号：US14824507
申请日：2015-08-12
Applicant: QUALCOMM Incorporated
Inventor： Wei-Chuan Chen , Yu Lu , Chando Park , Seung Hyuk Kang
CPC classification number: H01L43/12 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: Shadow-effect compensated fabrication of magnetic tunnel junction (MTJ) semiconductor elements is disclosed. Providing shadow-effect compensated fabrication of MTJ elements can provide reduced free layer sizing for enhanced MTJ operational margin. In certain aspects, to reduce size of a free layer during fabrication of an MTJ to provide enhanced write and retention symmetry, ion beam etching (IBE) fabrication process is employed to fabricate a free layer smaller than the pinned layer. To avoid asymmetrical footing being fabricated in free layer due to shadow-effect of neighboring MTJs, an ion beam directed at the MTJ is shadow-effect compensated. The angle of incidence of the ion beam directed at the MTJ is varied as the MTJ is rotated to be less steep when another MTJ is in directional line of the ion beam and the MTJ being fabricated. Thus, the free layer is etched more uniformly in the MTJ while avoiding increased etching damage.
-
5.发明申请PROCESS AND APPARATUS FOR TRANSFORMING NITRIDATION/OXIDATION AT EDGES, AND PROTECTING EDGES OF MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) LAYERS 审中-公开用于改变边缘处的氧化/氧化的过程和装置，以及保护磁性隧道结（MTJ）层的边缘公开(公告)号：US20140203381A1
公开(公告)日：2014-07-24
申请号：US13748979
申请日：2013-01-24
Applicant: QUALCOMM INCORPORATED
Inventor： Xiaochun Zhu , Xia Li , Wei-Chuan Chen , Seung H. Kang
Abstract: Material surrounding a magnetic tunnel junction (MTJ) device region of a multi-layer starting structure is etched, forming an MTJ device pillar having an MTJ layer with a chemically damaged peripheral edge region. De-nitridation or de-oxidation, or both, restore the chemically damaged peripheral region to form an edge-restored MTJ layer. An MTJ edge restoration assist layer is formed on the edge-restored MTJ layer. An MTJ-edge-protect layer is formed on the insulating MTJ-edge-restoration-assist layer.
Abstract translation: 蚀刻围绕多层起始结构的磁性隧道结（MTJ）器件区域的材料，形成具有化学损伤的外围边缘区域的MTJ层的MTJ器件柱。 脱氮或脱氧，或两者恢复化学损伤的外围区域，形成边缘恢复的MTJ层。 在边缘恢复的MTJ层上形成MTJ边缘恢复辅助层。 在绝缘MTJ边缘恢复辅助层上形成MTJ边缘保护层。
-
Patent Agency Ranking
公开(公告)号：US20140027869A1
公开(公告)日：2014-01-30
申请号：US13770526
申请日：2013-02-19
Applicant: QUALCOMM INCORPORATED
Inventor： Kangho Lee , Wei-Chuan Chen , Seung H. Kang
CPC classification number: H01L43/10 , G11C11/15 , G11C11/16 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.
Abstract translation: 垂直磁隧道结（MTJ）装置包括沉积在隧道势垒层和参考层之间的隧道磁阻（TMR）增强缓冲层。在TMR增强缓冲层和参考层之间沉积非晶合金间隔物以增强TMR非晶态 合金间隔块阻挡面心立方（fcc）取向钉扎层的模板效应，并且在钉扎层和TMR增强缓冲层之间提供强耦合，以确保完全垂直磁化。
-
公开(公告)号：US10582609B2
公开(公告)日：2020-03-03
申请号：US15798071
申请日：2017-10-30
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie Yun , Jonghae Kim , Xiaoju Yu , Mario Francisco Velez , Wei-Chuan Chen , Niranjan Sunil Mudakatte , Matthew Michael Nowak , Christian Hoffmann , Rodrigo Pacher Fernandes , Manuel Hofer , Peter Bainschab , Edgar Schmidhammer , Stefan Leopold Hatzl
Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.
-
公开(公告)号：US10534047B2
公开(公告)日：2020-01-14
申请号：US15474339
申请日：2017-03-30
Applicant: QUALCOMM Incorporated
Inventor： Wei-Chuan Chen , Wah Nam Hsu , Xia Li , Seung Hyuk Kang , Nicholas Ka Ming Stevens-Yu
Abstract: Tunnel magneto-resistive (TMR) sensors employing TMR devices with different magnetic field sensitivities for increased detection sensitivity are disclosed. For example, a TMR sensor may be used as a biosensor to detect the presence of biological materials. In aspects disclosed herein, free layers of at least two TMR devices in a TMR sensor are fabricated to exhibit different magnetic properties from each other (e.g., MR ratio, magnetic anisotropy, coercivity) so that each TMR device will exhibit a different change in resistance to a given magnetic stray field for increased magnetic field detection sensitivity. For example, the TMR devices may be fabricated to exhibit different magnetic properties such that one TMR device exhibits a greater change in resistance in the presence of a smaller magnetic stray field, and another TMR device exhibits a greater change in resistance in the presence of a larger magnetic stray field.
-
公开(公告)号：US20190147930A1
公开(公告)日：2019-05-16
申请号：US16247247
申请日：2019-01-14
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Wei-Chuan Chen , Wah Nam Hsu , Seung Hyuk Kang
Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
-
公开(公告)号：US20190019564A1
公开(公告)日：2019-01-17
申请号：US15817474
申请日：2017-11-20
Applicant: QUALCOMM Incorporated
Inventor： Xia Li , Seung Hyuk Kang , Wei-Chuan Chen
IPC: G11C16/34 , G11C14/00 , G11C11/56 , G11C16/04 , H01L27/108 , H01L29/792 , H01L45/00
Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.
-
-
-
-
-
-
-
-
-
Search Results
45
records
(took 0.028 seconds)
