公开(公告)号：US10109332B2

公开(公告)日：2018-10-23

申请号：US15704672

申请日：2017-09-14

Applicant: Kabushiki Kaisha Toshiba

Inventor： Mariko Shimizu ,  Yuichi Ohsawa ,  Hideyuki Sugiyama ,  Satoshi Shirotori ,  Altansargai Buyandalai ,  Yushi Kato

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation.

公开(公告)号：US09842635B2

公开(公告)日：2017-12-12

申请号：US15063808

申请日：2016-03-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hideyuki Sugiyama ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC: G11C11/16 ,  G11C11/15 ,  H01L29/66 ,  H03K19/18

CPC classification number: G11C11/161 ,  G11C11/15 ,  G11C11/165 ,  H01L29/66984 ,  H03K19/18

Abstract: A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.

公开(公告)号：US08981436B2

公开(公告)日：2015-03-17

申请号：US14041055

申请日：2013-09-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshiaki Saito ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Tetsufumi Tanamoto

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/94 ,  H01L29/82 ,  H01L21/00 ,  H01L43/10 ,  H01L29/66 ,  H03K19/173 ,  H03K19/18 ,  H03K19/177

CPC classification number: H01L43/10 ,  H01L29/66984 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/18

Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.

Abstract translation: 根据实施例的堆叠结构包括：半导体层; 形成在所述半导体层上的第一层，所述第一层含有选自Zr，Ti和Hf中的至少一种元素，所述第一层不比单原子层薄，并且不比五原子层厚; 形成在所述第一层上的隧道势垒层; 以及形成在隧道势垒层上的磁性层。

公开(公告)号：US10811067B2

公开(公告)日：2020-10-20

申请号：US16119003

申请日：2018-08-31

Applicant: Kabushiki Kaisha Toshiba

Inventor： Altansargai Buyandalai ,  Satoshi Shirotori ,  Yuichi Ohsawa ,  Hideyuki Sugiyama ,  Mariko Shimizu ,  Hiroaki Yoda ,  Katsuhiko Koui

IPC: G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes first and second regions, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first and second magnetic layers. The second region includes first to third conductive portions. A direction from the first conductive portion toward the second conductive portion is aligned with a third direction. The third direction crosses a plane including the first and second directions. The third conductive portion is between the first and second conductive portions in the third direction.

公开(公告)号：US10797229B2

公开(公告)日：2020-10-06

申请号：US16423805

申请日：2019-05-28

Applicant: Kabushiki Kaisha Toshiba

Inventor： Altansargai Buyandalai ,  Satoshi Shirotori ,  Yuichi Ohsawa ,  Hideyuki Sugiyama ,  Mariko Shimizu ,  Hiroaki Yoda ,  Tomoaki Inokuchi

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.

公开(公告)号：US20200090718A1

公开(公告)日：2020-03-19

申请号：US16351745

申请日：2019-03-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Katsuhiko KOUI ,  Hiroaki Yoda ,  Tomoaki Inokuchi ,  Naoharu Shimomura ,  Hideyuki Sugiyama

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08

Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.

公开(公告)号：US10361358B2

公开(公告)日：2019-07-23

申请号：US15704867

申请日：2017-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiko Abe ,  Kazutaka Ikegami ,  Shinobu Fujita ,  Katsuhiko Koui ,  Tomoaki Inokuchi ,  Satoshi Shirotori ,  Yuichi Ohsawa ,  Hideyuki Sugiyama ,  Hiroaki Yoda ,  Naoharu Shimomura ,  Yuuzo Kamiguchi

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.

公开(公告)号：US09570137B2

公开(公告)日：2017-02-14

申请号：US15067586

申请日：2016-03-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/08 ,  H03K19/16 ,  H01L27/22

CPC classification number: G11C11/165 ,  G11C11/161 ,  G11C11/1675 ,  G11C2013/0071 ,  H01L27/228 ,  H01L43/08 ,  H03K19/16

Abstract: A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second resistance state and includes a first ferromagnetic layer and a second ferromagnetic layer. The load resistance unit is electrically connected to the magnetoresistive device. The load resistance unit is in a first state and a second state. Differential resistance of the load resistance unit at the second state is lower than differential resistance of the load resistance unit at the first state.

Abstract translation: 磁存储器包括磁阻器件和负载电阻单元。 磁阻器件具有第一电阻状态和第二电阻状态，并且包括第一铁磁层和第二铁磁层。 负载电阻单元电连接到磁阻器件。 负载电阻单元处于第一状态和第二状态。 负载电阻单元在第二状态下的差分电阻低于负载电阻单元在第一状态下的差分电阻。

公开(公告)号：US09520171B2

公开(公告)日：2016-12-13

申请号：US14832520

申请日：2015-08-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Yoshiaki Saito ,  Tetsufumi Tanamoto

IPC: G11C11/15 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08

Abstract: A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.

Abstract translation: 根据实施例的电阻变化存储器包括：存储单元，包括包括第一和第二端子的电阻变化元件和半导体元件，所述半导体元件包括第一导电类型的第一半导体层，第二半导体层 第一导电类型和与第一导电类型不同的第二导电类型的第三半导体层，第三半导体层设置在第一半导体层和第二半导体层之间，第一半导体层连接到第二导体类型 的电阻变化元件; 以及读取单元，被配置为通过在第一端子和第二半导体层之间施加第一读取电压来执行读取操作，然后在第一端子和第二半导体层之间施加低于第一读取电压的第二读取电压 。

公开(公告)号：US10902900B2

公开(公告)日：2021-01-26

申请号：US16351745

申请日：2019-03-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Katsuhiko Koui ,  Hiroaki Yoda ,  Tomoaki Inokuchi ,  Naoharu Shimomura ,  Hideyuki Sugiyama

IPC: H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.