公开(公告)号：US10573528B2

公开(公告)日：2020-02-25

申请号：US15842841

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Fee Li Lie ,  Dongbing Shao ,  Robert Wong ,  Yongan Xu

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/78

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

公开(公告)号：US10573520B2

公开(公告)日：2020-02-25

申请号：US16006270

申请日：2018-06-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  G03F7/09

Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a plurality of mandrels from a base structure, forming a plurality of non-mandrels including a hard mask material having an etch property substantially similar to that of the plurality of mandrels, forming photo-sensitive material or a memorization layer over the plurality of mandrels and the plurality of non-mandrels, and applying an exposure scheme to the photo-sensitive material or the memorization layer to create at least one mandrel cut pattern and at least one non-mandrel cut pattern.

公开(公告)号：US20190378718A1

公开(公告)日：2019-12-12

申请号：US16006270

申请日：2018-06-12

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  G03F7/09

Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a plurality of mandrels from a base structure, forming a plurality of non-mandrels including a hard mask material having an etch property substantially similar to that of the plurality of mandrels, forming photo-sensitive material or a memorization layer over the plurality of mandrels and the plurality of non-mandrels, and applying an exposure scheme to the photo-sensitive material or the memorization layer to create at least one mandrel cut pattern and at least one non-mandrel cut pattern.

公开(公告)号：US20190341444A1

公开(公告)日：2019-11-07

申请号：US16456610

申请日：2019-06-28

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L49/02 ,  H01L21/3105

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

公开(公告)号：US10354885B2

公开(公告)日：2019-07-16

申请号：US15897390

申请日：2018-02-15

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC: H01L29/06 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3105

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

公开(公告)号：US20190121316A1

公开(公告)日：2019-04-25

申请号：US15789067

申请日：2017-10-20

Applicant: International Business Machines Corporation

Inventor： Richard C. Johnson ,  Hao Tang ,  Yongan Xu

IPC: G05B19/402

Abstract: Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

公开(公告)号：US09991365B1

公开(公告)日：2018-06-05

申请号：US15498112

申请日：2017-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xuefeng Liu ,  Peng Xu ,  Yongan Xu

IPC: H01L21/82 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/02238 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/7827

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

公开(公告)号：US20160358820A1

公开(公告)日：2016-12-08

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US09406746B2

公开(公告)日：2016-08-02

申请号：US14184229

申请日：2014-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

Abstract translation: 一种形成半导体器件的方法，包括在鳍结构的沟道部分上形成牺牲栅极结构，其中牺牲栅极结构的侧壁与鳍结构的沟道部分的上表面的交点处的角度为 钝。 外延源极和漏极区结构形成在鳍结构的源极区域和漏极区域部分上。 在牺牲栅极结构的侧壁上形成至少一种电介质材料。 可以去除牺牲栅极结构以为鳍结构的通道部分提供开口。 在开口中形成功能门结构。 由功能门结构的侧壁与翅片结构的通道部分的上表面的交点限定的至少一个角度是钝的。

公开(公告)号：US20140363969A1

公开(公告)日：2014-12-11

申请号：US13913823

申请日：2013-06-10

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

Abstract translation: 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔打开通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。