公开(公告)号：US20180350605A1

公开(公告)日：2018-12-06

申请号：US16058409

申请日：2018-08-08

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823487 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/7827

摘要： Embodiments are directed to a method of forming a feature of a semiconductor device. In one or more embodiments, the feature is a gate, and the method includes forming a substrate and forming a gate material extending over a major surface of the substrate. The method further includes forming a trench extending through the gate material and into the substrate in a first direction, wherein the trench further extends through the gate material and the substrate in a second direction. The method further includes filling the trench with a fill material and forming individual gates from the gate material, wherein the individual gates extend along a third direction.

公开(公告)号：US10134595B2

公开(公告)日：2018-11-20

申请号：US15474585

申请日：2017-03-30

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Sivananda K. Kanakasabapathy ,  Peng Xu

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/51 ,  H01L29/78

摘要： Embodiments are directed to a method of forming a feature of a semiconductor device. In one or more embodiments, the feature is a gate, and the method includes forming a substrate and forming a gate material extending over a major surface of the substrate. The method further includes forming a trench extending through the gate material and into the substrate in a first direction, wherein the trench further extends through the gate material and the substrate in a second direction. The method further includes filling the trench with a fill material and forming individual gates from the gate material, wherein the individual gates extend along a third direction.

公开(公告)号：US20180286866A1

公开(公告)日：2018-10-04

申请号：US15995800

申请日：2018-06-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

IPC分类号： H01L27/108 ,  H01L29/51 ,  H01L29/06 ,  H01L29/04 ,  H01L49/02 ,  H01L27/12 ,  G06F17/50 ,  H01L21/84

CPC分类号： H01L27/10832 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0733 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1203 ,  H01L27/1211 ,  H01L28/40 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/945

摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

公开(公告)号：US10043760B2

公开(公告)日：2018-08-07

申请号：US15794637

申请日：2017-10-26

申请人： International Business Machines Corporation

发明人： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC分类号： H01L21/311 ,  H01L23/544 ,  H01L21/308 ,  G03F9/00 ,  G03F7/20 ,  H01L21/033

CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

摘要： Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

公开(公告)号：US10042968B2

公开(公告)日：2018-08-07

申请号：US15285520

申请日：2016-10-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin K. Chan ,  Sivananda K. Kanakasabapathy ,  Babar A. Khan ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Xinhui Wang

IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L29/78 ,  G06F17/50 ,  H01L21/84 ,  H01L29/66 ,  H01L29/94 ,  H01L27/12 ,  H01L49/02 ,  H01L29/04 ,  H01L27/07 ,  H01L27/06

摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

公开(公告)号：US20180151686A1

公开(公告)日：2018-05-31

申请号：US15878452

申请日：2018-01-24

申请人： International Business Machines Corporation

发明人： Emre Alptekin ,  Veeraraghavan S. Basker ,  Sivananda K. Kanakasabapathy

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/06 ,  H01L23/535

CPC分类号： H01L29/665 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.

公开(公告)号：US20180122708A1

公开(公告)日：2018-05-03

申请号：US15608545

申请日：2017-05-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Andrew M. Greene ,  Balasubramanian S. Pranatharthiharan ,  Sivananda K. Kanakasabapathy ,  John R. Sporre

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/0886 ,  H01L21/0271 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/12 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785

摘要： A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.

公开(公告)号：US09934970B1

公开(公告)日：2018-04-03

申请号：US15403371

申请日：2017-01-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC分类号： H01L29/40 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/31 ,  H01L21/027 ,  H01L45/00 ,  H01L21/28 ,  H01L51/00

CPC分类号： H01L21/0337 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L45/1675 ,  H01L51/0018 ,  H01L2224/0362 ,  H01L2224/11622

摘要： A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US20180090384A1

公开(公告)日：2018-03-29

申请号：US15478822

申请日：2017-04-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Zhenxing Bi ,  Donald F. Canaperi ,  Thamarai S. Devarajan ,  Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Peng Xu

IPC分类号： H01L21/8234 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/823481 ,  H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

公开(公告)号：US09929016B2

公开(公告)日：2018-03-27

申请号：US15679433

申请日：2017-08-17

申请人： International Business Machines Corporation

发明人： Sivananda K. Kanakasabapathy ,  Ahmet S. Ozcan

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/263 ,  H01J37/304 ,  H01J37/30 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/2633 ,  H01J37/3005 ,  H01J37/304 ,  H01L21/26566 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/26 ,  H01L29/66795 ,  H01L29/785

摘要： A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process.