公开(公告)号：US08817533B2

公开(公告)日：2014-08-26

申请号：US13487427

申请日：2012-06-04

Applicant: Kailash Gopalakrishnan

Inventor： Kailash Gopalakrishnan

IPC: G11C11/00

CPC classification number: H01L27/2409 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/224

Abstract: A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.

Abstract translation: 已经示出了具有多个位线和字线的交叉点阵列; 以及多个横杆元件，其中每个横杆元件设置在位线和字线之间，并且每个横杆元件至少具有用作与对称或基本上对称的电阻性存储器节点串联的整流器的固体电解质材料。 交叉开关元件响应于以下电压：将交叉开关元件中的固体电解质从OFF状态转变到导通状态的第一组电压，用于读取或编程对称电阻性存储器的第二组电压，以及第三组 一组电压将固体电解质从ON状态转变为OFF状态。

公开(公告)号：US20140022850A1

公开(公告)日：2014-01-23

申请号：US13551597

申请日：2012-07-17

Applicant: Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

Inventor： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC: G11C7/10

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C2213/71 ,  G11C2213/72

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.

Abstract translation: 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 该系统包括电耦合到多个列电压的列电压开关。 列电压开关包括电耦合到双向存取二极管的输出。 多个列电压包括至少一个选择列电压和一个取消选择列电压。 该系统包括电耦合到多个行电压的行电压开关。 行电压开关包括电耦合到双向存取二极管的输出。 多个行电压包括至少一个选择行电压和一个取消选择行电压。 该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。

公开(公告)号：US07763932B2

公开(公告)日：2010-07-27

申请号：US11427487

申请日：2006-06-29

Applicant: Kailash Gopalakrishnan ,  Rohit Sudhir Shenoy

Inventor： Kailash Gopalakrishnan ,  Rohit Sudhir Shenoy

IPC: H01L27/115

CPC classification number: H01L27/0207 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42336 ,  H01L29/785 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/936

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract translation: 一种结构，使用该结构的存储器件以及该结构的制造方法。 该结构包括：纳米鳍片阵列，每个纳米鳍片包括沿着第一方向轴向延伸的细长的半导体材料块，所述纳米鳍片分别以至少两个纳米翅片的组排列，其中， 每个相邻组的纳米翅片的翅片在阵列的第一和第二侧上彼此相交; 其中每组纳米鳍片的纳米鳍片电连接到对于每组纳米鳍片特有的公共接触点，使得所述公共接触件包括在所述阵列的第一侧上的第一公共接触点和第二公共接触点 在阵列的第二面; 并且其中每组纳米鳍具有至少两个门，其电控制每组纳米鳍的纳米鳍的电导。

公开(公告)号：US20090102538A1

公开(公告)日：2009-04-23

申请号：US12338275

申请日：2008-12-18

Applicant: Hemantha Kumar Wickramasinghe ,  Kailash Gopalakrishnan

Inventor： Hemantha Kumar Wickramasinghe ,  Kailash Gopalakrishnan

IPC: H03K17/00

CPC classification number: H01L27/1203 ,  G11C16/08 ,  H01L21/84 ,  H01L27/115 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract translation: 电子扫描复用设备能够寻址易失性或非易失性存储器单元内的多个位。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。

公开(公告)号：US20080304307A1

公开(公告)日：2008-12-11

申请号：US11761043

申请日：2007-06-11

Applicant: Kailash Gopalakrishnan

Inventor： Kailash Gopalakrishnan

IPC: G11C11/21 ,  G11C5/02

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/76

Abstract: A symmetrically resistive memory material (such as a phase change material) is described for use as a rectifying element for driving symmetric or asymmetric resistive memory elements in a crosspoint memory architecture. The crosspoint architecture has a plurality of electrodes and a plurality of crossbar elements, with each crossbar element being disposed between a first and a second electrode. The crossbar element is made of a symmetric resistive memory element used as a rectifier in series with a symmetric or asymmetric resistive memory element.

Abstract translation: 描述了对称电阻存储器材料（例如相变材料），用作在交叉点存储器架构中用于驱动对称或非对称电阻存储器元件的整流元件。 交叉点结构具有多个电极和多个横杆元件，每个横杆元件设置在第一和第二电极之间。 交叉开关元件由用作与对称或不对称电阻存储器元件串联的整流器的对称电阻存储器元件制成。

公开(公告)号：US07352029B2

公开(公告)日：2008-04-01

申请号：US11117276

申请日：2005-04-27

Applicant: Hemantha Kumar Wickramasinghe ,  Kailash Gopalakrishnan

Inventor： Hemantha Kumar Wickramasinghe ,  Kailash Gopalakrishnan

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/1203 ,  G11C16/08 ,  H01L21/84 ,  H01L27/115 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract translation: 电子扫描复用设备能够寻址易失性或非易失性存储器单元内的多个位。 多路复用装置产生具有两个相对形成的耗尽区的电子扫描导电通道。 每个耗尽区的耗尽宽度由施加到多路复用器件每端的相应控制栅极的电压控制。 目前的多位寻址技术允许例如在单个节点上访问或寻址10到100位的数据。 本发明还可用于构建可编程纳米尺度逻辑阵列或用于随机访问纳米级传感器阵列。

公开(公告)号：US07304327B1

公开(公告)日：2007-12-04

申请号：US10706162

申请日：2003-11-12

Applicant: Farid Nemati ,  Kailash Gopalakrishnan ,  Andrew E. Horch

Inventor： Farid Nemati ,  Kailash Gopalakrishnan ,  Andrew E. Horch

IPC: H01L29/745

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: Switching operations, such as those used in memory devices, are enhanced using a semiconductor device having a thyristor adapted to switch between conducting and blocking states and operate at low power. According to an example embodiment of the present invention, thyristor characteristics are managed over a broad temperature range using a control circuit for coupling a signal, such as a DC voltage signal, to a portion of a thyristor for controlling temperature-related operation thereof, e.g., for controlling bipolar gains. In one implementation, a control port adaptively adjusts a signal coupled to the thyristor as a function of temperature, such that at relatively low temperatures unwanted increases in holding current (IH) are prevented. In another implementation, the control port couples the signal at relatively high temperature operation for controlling the forward blocking voltage (VFB) in such a manner that a blocking state of the thyristor is held. In still another implementation, a circuit controller is adapted for applying the signal to the thyristor via the control port as a function of temperature by monitoring operation of a reference thyristor. With these approaches, thyristor operation can be maintained in a relatively stable manner over a broad temperature range.

Abstract translation: 使用具有适于在导通和阻塞状态之间切换并且以低功率操作的晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。 根据本发明的示例性实施例，使用用于将诸如DC电压信号的信号耦合到用于控制其温度相关操作的晶闸管的一部分的控制电路，在宽温度范围内管理晶闸管特性，例如 ，用于控制双极增益。 在一个实施方案中，控制端口自适应地调节作为温度的函数耦合到晶闸管的信号，使得在相对较低的温度下，防止了保持电流（I H H）的不期望的增加。 在另一实施方案中，控制端口以相对较高的温度操作耦合信号，以便控制可控硅晶闸管的阻塞状态的方式来控制正向阻断电压（V SUB FB）。 在另一个实施方式中，电路控制器适于通过监视参考晶闸管的操作，通过控制端口将信号作为温度的函数施加到晶闸管。 利用这些方法，可以在宽的温度范围内以相对稳定的方式保持晶闸管操作。

公开(公告)号：US20140022851A1

公开(公告)日：2014-01-23

申请号：US13584423

申请日：2012-08-13

Applicant: Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

Inventor： Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li ,  Robert K. Montoye

IPC: G11C7/10

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/004 ,  G11C2213/71 ,  G11C2213/72

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

Abstract translation: 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

公开(公告)号：US20130223125A1

公开(公告)日：2013-08-29

申请号：US13407848

申请日：2012-02-29

Applicant: John K. DeBrosse ,  Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li

Inventor： John K. DeBrosse ,  Kailash Gopalakrishnan ,  Chung H. Lam ,  Jing Li

IPC: G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C13/0069 ,  G11C5/025 ,  G11C8/10 ,  G11C8/14 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0023 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77

Abstract: A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.

Abstract translation: 一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。 该系统包括列电压。 列电压开关包括列电压和电耦合到双向存取二极管的输出。 列电压包括至少一个写一列电压和至少一个写零列电压。 该系统还包括行电压开关。 行电压开关包括行电压和电耦合到双向存取二极管的输出。 行电压包括至少一个写入一行电压和至少一个写入零行电压。 该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。 该系统包括电耦合到行和列开关的选择线的写入驱动器。

公开(公告)号：US08203873B2

公开(公告)日：2012-06-19

申请号：US12110644

申请日：2008-04-28

Applicant: Kailash Gopalakrishnan

Inventor： Kailash Gopalakrishnan

IPC: G11C11/00

CPC classification number: H01L27/2409 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/224

Abstract: An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired.

Abstract translation: 描述了一种不对称编程的记忆材料（例如固体电解质材料），用作整流元件，用于驱动交叉点存储器架构中的对称或基本对称的电阻性存储器元件。 固体电解质元件（SE）在OFF状态下具有非常高的电阻，并且在ON状态下具有非常低的电阻（因为它是处于ON状态的金属灯丝）。 这些属性使其成为接近理想的二极管。 在存储元件的电流（在编程/读取/擦除期间）期间，固体电解质材料也编程成低电阻状态。 固体电解质材料的最终状态被还原成高电阻状态，同时确保记忆材料的最终状态是期望的。