公开(公告)号：US11994801B2

公开(公告)日：2024-05-28

申请号：US17319785

申请日：2021-05-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Giwoong Nam ,  Junghwan Jang ,  Inhee Hwang ,  Taekyu Choi ,  Sanghyun Park

IPC: G03F7/16 ,  B05C11/06 ,  H01L21/02

CPC classification number: G03F7/168 ,  B05C11/06 ,  G03F7/162 ,  G03F7/164 ,  H01L21/0209

Abstract: A semiconductor manufacturing device has an outer cup and inner cup with a wafer suction mount disposed within the outer cup. A photoresist material is applied to a first surface of a semiconductor wafer disposed on the wafer suction mount while rotating at a first speed. A gas port is disposed on the inner cup for dispensing a gas oriented toward a bottom side of the semiconductor wafer. The gas port purges a second surface of the semiconductor wafer with a gas to remove contamination. The second surface of the semiconductor wafer is rinsed while purging with the gas. The gas can be a stable or inert gas, such as nitrogen. The contamination is removed from the second surface of the semiconductor wafer through an outlet between the inner cup and outer cup. The semiconductor wafer rotates at a second greater speed after discontinuing purge with the gas.

公开(公告)号：US20240096736A1

公开(公告)日：2024-03-21

申请号：US17932987

申请日：2022-09-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HyunSeok Park

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367 ,  H01L25/16

CPC classification number: H01L23/3733 ,  H01L21/4882 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3737 ,  H01L25/165 ,  H01L24/16

Abstract: A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.

公开(公告)号：US20240096634A1

公开(公告)日：2024-03-21

申请号：US18469523

申请日：2023-09-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： IkSoo JI ,  SooYeon HAN

IPC: H01L21/304 ,  H01L21/78 ,  H01L23/528

CPC classification number: H01L21/304 ,  H01L21/78 ,  H01L23/528

Abstract: A method for singulating a semiconductor substrate into individual semiconductor devices, comprising: providing a semiconductor substrate having a front surface and a back surface, wherein the semiconductor substrate comprises device regions that are separated from each other by respective predetermined saw streets; forming an interconnect layer on the front surface; etching the front surface at the predetermined saw streets to form respective frontside openings each having a first depth, wherein the first depth is smaller than a thickness of the semiconductor substrate; attaching a semiconductor element onto the front surface in each device region; and etching the back surface at the respective predetermined saw streets to form respective backside openings each having a second depth, wherein each frontside opening is at least partially aligned with the backside opening at the same saw street to singulate the device regions of the semiconductor substrate into individual semiconductor devices.

公开(公告)号：US20240088060A1

公开(公告)日：2024-03-14

申请号：US18517859

申请日：2023-11-22

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： GunHyuck Lee

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L24/20 ,  H01L25/0652 ,  H01L2224/2205 ,  H01L2924/3025

Abstract: A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.

公开(公告)号：US11923260B2

公开(公告)日：2024-03-05

申请号：US18154993

申请日：2023-01-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  ChangOh Kim

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/60 ,  H01L23/66

CPC classification number: H01L23/31 ,  H01L21/565 ,  H01L23/60 ,  H01L23/66

Abstract: A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

公开(公告)号：US20240063196A1

公开(公告)日：2024-02-22

申请号：US17820156

申请日：2022-08-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： TaeKeun Lee ,  Hyunil Bae

IPC: H01L25/16 ,  H01L23/552 ,  H01L23/367 ,  H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/165 ,  H01L23/552 ,  H01L23/3675 ,  H01L23/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/3025 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/16235 ,  H01L2224/13655 ,  H01L2224/13582 ,  H01L2224/1601 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L24/48 ,  H01L2224/48227 ,  H01L25/0657

Abstract: A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.

公开(公告)号：US20240021536A1

公开(公告)日：2024-01-18

申请号：US17812339

申请日：2022-07-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung ,  OMin Kwon

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/66 ,  H01L21/4853 ,  H01L21/565 ,  H01L2223/6677

Abstract: A semiconductor device has a substrate and encapsulant deposited over the substrate. An electrical connector is disposed over the substrate outside the encapsulant. An antenna can be formed over the substrate. A first shielding material is disposed over a portion of the encapsulant without covering the electrical connector with the first shielding material. The first shielding material is disposed over the portion of the encapsulant and the portion of the substrate using a direct jet printer. A cover is disposed over the electrical connector. A second shielding material is disposed over the encapsulant to prevent the second shielding material from reaching the electrical connector. The second shielding material overlaps the first shielding material and covers a side surface of the encapsulant and a side surface of the substrate. The cover is removed to expose the electrical connector free of shielding material.

公开(公告)号：US20240014093A1

公开(公告)日：2024-01-11

申请号：US17810901

申请日：2022-07-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung ,  OMin Kwon ,  HeeSoo Lee

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/433

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/4334

Abstract: A semiconductor device has a first substrate and electrical component disposed over the first substrate. A graphene layer is disposed over the electrical component, and a thermal interface material is disposed between the graphene layer. A heat sink is disposed over the thermal interface material. The graphene layer, in combination with the thermal interface material, aids with the heat transfer between the electrical component and heat sink. The graphene layer may be disposed over a second substrate made of copper. An encapsulant is deposited over the first substrate and around the electrical component and graphene substrate. The thermal interface material and heat sink may extend over the encapsulant. The heat sink can have vertical or angled extensions from the horizontal portion of the heat sink down to the substrate. The heat sink can extend over multiple modules.

公开(公告)号：US11862572B2

公开(公告)日：2024-01-02

申请号：US18161693

申请日：2023-01-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  SeongHwan Park ,  JinHee Jung

IPC: H01L23/552 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01Q1/22

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66 ,  H01Q1/2283

Abstract: A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.

公开(公告)号：US20230420382A1

公开(公告)日：2023-12-28

申请号：US17808613

申请日：2022-06-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung ,  YoungCheol Kim

IPC: H01L23/552 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L25/165 ,  H01L24/96 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/3025 ,  H01L24/97

Abstract: A semiconductor device has a substrate. A first electrical component and second electrical component are disposed over the substrate. A conductive pillar is formed over the substrate between the first electrical component and second electrical component. A first shielding layer is formed over the first electrical component and conductive pillar by jet printing conductive material. A second shielding layer is formed over the first electrical component and second electrical component by sputtering, spraying, or plating conductive material. An insulating layer is optionally formed between the first shielding layer and second shielding layer by jet printing insulating material over the first shielding layer.