公开(公告)号：US20240332035A1

公开(公告)日：2024-10-03

申请号：US18193942

申请日：2023-03-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SuJeong Kwon

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L21/565 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2225/06548

Abstract: A semiconductor device has a substrate and a first electrical component disposed over the substrate. A first encapsulant is deposited over the first electrical component and substrate. An interconnect structure including a graphene core shell is formed over or through the first encapsulant. The graphene core shell has a copper core or silver core. The interconnect structure has a plurality of cores covered by graphene and the graphene is interconnected within the interconnect structure to form an electrical path. The interconnect structure has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. A second electrical component is disposed over the first encapsulant. A second encapsulant is deposited over the second electrical component. A shielding layer is formed over the second encapsulant. The shielding layer can have a graphene core shell.

公开(公告)号：US20240312884A1

公开(公告)日：2024-09-19

申请号：US18184649

申请日：2023-03-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SeungHyun Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3128 ,  H01L25/18

Abstract: A semiconductor device has a substrate and an electrical component disposed over a first surface of the substrate. A first encapsulant is deposited over the first surface of the substrate. A second encapsulant is deposited over a second surface of the substrate with a via formed in the second encapsulant. A conductive material containing a graphene core shell is deposited in the via in the second encapsulant to form a conductive post. The graphene core shell can have a copper core with a graphene coating formed over the copper core. The conductive material has a matrix to embed the graphene core shell. The conductive material can have a plurality of cores covered by graphene and the graphene is interconnected within the conductive material to form an electrical path. The conductive material can have thermoset material or polymer or composite epoxy type matrix to embed the graphene core shell.

公开(公告)号：US20240321768A1

公开(公告)日：2024-09-26

申请号：US18188720

申请日：2023-03-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HeeYoun Kim

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L23/29 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6661 ,  H01L2224/16227 ,  H01L2924/186 ,  H01L2924/3025

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.

公开(公告)号：US20240234291A1

公开(公告)日：2024-07-11

申请号：US18150567

申请日：2023-01-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HyunSeok Park ,  KyoWang Koo ,  Sinjae Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/49877 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49894 ,  H01L25/16 ,  H01L24/16

Abstract: A semiconductor device has a one-layer interconnect substrate and electrical component disposed over a first surface of the interconnect substrate. The electrical components can be discrete electrical devices, IPDs, semiconductor die, semiconductor packages, surface mount devices, and RF components. An RDL with a graphene core shell is formed over a second surface of the interconnect substrate. The graphene core shell has a copper core and a graphene coating formed over the copper core. The RDL further has a matrix to embed the graphene core shell. The graphene core shells through RDL form an electrical path. The RDL can be thermoset material or polymer or composite epoxy type matrix. The graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. The RDL with graphene core shell is useful for electrical conductivity and electrical interconnect within an SIP.

公开(公告)号：US20240096736A1

公开(公告)日：2024-03-21

申请号：US17932987

申请日：2022-09-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  HyunSeok Park

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367 ,  H01L25/16

CPC classification number: H01L23/3733 ,  H01L21/4882 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3737 ,  H01L25/165 ,  H01L24/16

Abstract: A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.

公开(公告)号：US20250022792A1

公开(公告)日：2025-01-16

申请号：US18351300

申请日：2023-07-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SuJeong Kwon

IPC: H01L23/498 ,  H01L21/324 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device has a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A conductive layer is formed over the substrate opposite the electrical component after depositing the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.

公开(公告)号：US20240413095A1

公开(公告)日：2024-12-12

申请号：US18329871

申请日：2023-06-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SuJeong Kwon

IPC: H01L23/552 ,  H01L21/324 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component. A shielding layer is formed over the encapsulant. The shielding layer includes a plurality of graphene-coated metal balls in a matrix. The shielding layer is sintered using intensive pulsed light (IPL) radiation.

公开(公告)号：US20240194628A1

公开(公告)日：2024-06-13

申请号：US18064149

申请日：2022-12-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SuJeong Kwon

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L24/29 ,  H01L23/3737 ,  H01L23/49805 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/162 ,  H01L23/49816 ,  H01L24/49 ,  H01L2224/27452 ,  H01L2224/2929 ,  H01L2224/29347 ,  H01L2224/29493 ,  H01L2224/29499 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/3511

Abstract: A semiconductor device has a substrate and an adhesive layer with a graphene core shell deposited over a surface of the substrate. An electrical component is affixed to the substrate with the adhesive layer. A bond wire is connected between the electrical component and substrate. The graphene core shell has a copper core and graphene coating over the copper core. The graphene coated core shell is embedded within a matrix. The graphene core shells within the adhesive layer to form a thermal path. The matrix can be a thermoset material or polymer or composite epoxy type matrix. The graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. The adhesive layer with graphene core shell is useful for die attachment. The graphene core adhesive layer provides exceptional heat dissipation, shock absorption, and vibration dampening.

公开(公告)号：US20240379480A1

公开(公告)日：2024-11-14

申请号：US18315964

申请日：2023-05-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  SeongKuk Kim ,  SinJae Kim ,  SeokBeom Heo

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L23/552

Abstract: A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.

公开(公告)号：US20240234292A1

公开(公告)日：2024-07-11

申请号：US18150634

申请日：2023-01-05

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  EunHee Myung

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/49877 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/105 ,  H01L25/162 ,  H01L25/165 ,  H01L24/16

Abstract: A semiconductor device includes a first substrate and a second substrate. A graphene-coated interconnect is disposed between the first substrate and second substrate. A semiconductor die is disposed between the first substrate and second substrate. The first substrate is electrically coupled to the second substrate through the graphene-coated interconnect. An encapsulant is deposited between the first substrate and second substrate.