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公开(公告)号:US12046554B2
公开(公告)日:2024-07-23
申请号:US17672325
申请日:2022-02-15
发明人: Shih-Pang Chang , Haw-Yun Wu , Yao-Chung Chang , Chun-Lin Tsai
IPC分类号: H01L23/528 , H01L23/522 , H01L29/40 , H01L29/417 , H01L29/423
CPC分类号: H01L23/528 , H01L23/5226 , H01L29/401 , H01L29/41758 , H01L29/4238
摘要: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.
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公开(公告)号:US12046510B2
公开(公告)日:2024-07-23
申请号:US17339082
申请日:2021-06-04
发明人: Wei-Yip Loh , Chih-Wei Chang , Hong-Mao Lee , Chun-Hsien Huang , Yu-Ming Huang , Yan-Ming Tsai , Yu-Shiuan Wang , Hung-Hsu Chen , Yu-Kai Chen , Yu-Wen Cheng
IPC分类号: H01L21/768 , H01L21/8234 , H01L23/522 , H01L29/08 , H01L29/417 , H01L29/66 , H01L21/285 , H01L29/78
CPC分类号: H01L21/76856 , H01L21/76805 , H01L21/823425 , H01L21/823475 , H01L23/5226 , H01L29/0847 , H01L29/41791 , H01L29/66795 , H01L21/28518 , H01L29/785
摘要: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
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公开(公告)号:US20240244843A1
公开(公告)日:2024-07-18
申请号:US18618451
申请日:2024-03-27
发明人: Seung Hyun CHO , Kwang Ho LEE , Ji Hwan YU , Jong Soo KIM
IPC分类号: H10B43/27 , H01L21/768 , H01L23/522 , H01L23/528 , H10B43/10 , H10B43/35
CPC分类号: H10B43/27 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H10B43/10 , H10B43/35
摘要: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
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124.
公开(公告)号:US20240243058A1
公开(公告)日:2024-07-18
申请号:US18155890
申请日:2023-01-18
发明人: Bong Woong Mun , Jeoung Mo Koo
IPC分类号: H01L23/522 , H01L21/762
CPC分类号: H01L23/5227 , H01L21/762 , H01L23/5226 , H01L28/10
摘要: A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.
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公开(公告)号:US20240243057A1
公开(公告)日:2024-07-18
申请号:US18124591
申请日:2023-03-22
发明人: Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai
IPC分类号: H01L23/522 , H01L21/768 , H01L23/00 , H01L27/08
CPC分类号: H01L23/5223 , H01L21/76805 , H01L23/5226 , H01L24/05 , H01L24/11 , H01L27/0805 , H01L2224/05026 , H01L2224/116 , H01L2924/19041 , H01L2924/30105
摘要: An integrated circuit includes a substrate, an interconnection layer, an insulation layer, a metal bump structure, and a metal-insulator-metal capacitor. The interconnection layer is disposed above the substrate. The interconnection layer includes an interlayer dielectric layer and an interconnection structure disposed in the interlayer dielectric layer. The insulation layer is disposed on the interconnection layer, the metal bump structure is disposed on the insulation layer, and the metal-insulator-metal capacitor is disposed conformally on the metal bump structure and the insulation layer. A manufacturing method of the integrated circuit includes the following steps.
The interconnection layer is formed above the substrate. The insulation layer is formed on the interconnection layer, the metal bump structure is formed on the insulation layer, and the metal-insulator-metal capacitor is formed conformally on the metal bump structure and the insulation layer.-
公开(公告)号:US12040273B2
公开(公告)日:2024-07-16
申请号:US18047412
申请日:2022-10-18
发明人: Lin-Yu Huang , Sheng-Tsung Wang , Jia-Chuan You , Chia-Hao Chang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
IPC分类号: H01L23/532 , H01L21/768 , H01L23/522 , H01L29/40 , H01L29/417 , H01L29/78
CPC分类号: H01L23/53295 , H01L21/7682 , H01L23/5226 , H01L29/401 , H01L29/41791 , H01L29/785
摘要: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
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127.
公开(公告)号:US12040268B2
公开(公告)日:2024-07-16
申请号:US17830196
申请日:2022-06-01
发明人: Je-Hsiung Lan , Jonghae Kim , Kai Liu , Nosun Park
IPC分类号: H01L23/522 , H01C7/00 , H01C17/075 , H01L23/66 , H01L49/02
CPC分类号: H01L23/5228 , H01C7/006 , H01C17/075 , H01L23/5226 , H01L23/66 , H01L28/10 , H01L28/24 , H01L2223/6672
摘要: An integrated circuit (IC) includes a substrate and a thin film resistor (TFR) device structure. The TFR device structure includes a first portion of a first metallization layer and a second portion of the first metallization layer on the substrate. The TFR device structure also includes a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer. The TFR device structure further includes a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer. The TFR device structure also includes a first portion of a third metallization layer coupling the first portion of the second metallization layer to the second portion of the second metallization layer.
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公开(公告)号:US12040266B2
公开(公告)日:2024-07-16
申请号:US17460315
申请日:2021-08-30
发明人: Hungen Hsu , Wei-Tien Shen , Kuo-Ching Hsu
IPC分类号: H01L23/498 , H01L21/48 , H01L23/522 , H01L23/528 , H01L23/538 , H01L25/16 , H01L49/02
CPC分类号: H01L23/49838 , H01L21/4857 , H01L21/486 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/5223 , H01L23/5226 , H01L23/5283 , H01L23/5385 , H01L23/5386 , H01L25/165 , H01L28/60
摘要: Embodiments provide a package substrate. The package substrate includes a substrate having a cavity hole therein, and a semiconductor device in the cavity hole. The semiconductor device has first terminal side and a second terminal side opposite to the first terminal side. The package substrate further includes a first redistribution structure on the first terminal side of the cavity substrate to electrically couple to a first pad and a second pad on the first terminal side of the semiconductor device; and a second redistribution structure on the second side of the cavity substrate to electrically couple to a third pad and fourth pad on the second terminal side of the semiconductor device.
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公开(公告)号:US12040178B2
公开(公告)日:2024-07-16
申请号:US18307197
申请日:2023-04-26
发明人: Hsiu-Wen Hsueh , Yu-Hsiang Chen , Wen-Sheh Huang , Chii-Ping Chen , Wan-Te Chen
IPC分类号: H01L21/02 , H01L21/304 , H01L21/762 , H01L23/522 , H01L23/64 , H01L27/06 , H01L27/08 , H01L49/02 , H01L23/00 , H01L23/34 , H01L23/528
CPC分类号: H01L21/022 , H01L21/304 , H01L21/762 , H01L23/5228 , H01L23/647 , H01L27/0635 , H01L27/0802 , H01L28/24 , H01L23/345 , H01L23/5226 , H01L23/528 , H01L24/05 , H01L28/20 , H01L2924/1305
摘要: A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.
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公开(公告)号:US20240234637A1
公开(公告)日:2024-07-11
申请号:US18614750
申请日:2024-03-25
发明人: Chen-En Yen , Ming-Da Cheng , Mirng-Ji Lii , Wen-Hsiung Lu , Cheng-Jen Lin , Chin-Wei Kang , Chang-Jung Hsueh
IPC分类号: H01L33/42 , H01L23/522 , H01L33/60 , H01L33/62 , H10B63/00
CPC分类号: H01L33/42 , H01L23/5223 , H01L23/5226 , H01L33/60 , H01L33/62 , H10B63/80
摘要: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
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