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1.发明授权公开(公告)号：US11502193B2
公开(公告)日：2022-11-15
申请号：US17019836
申请日：2020-09-14
发明人： Bong Woong Mun , Upinder Singh , Jeoung Mo Koo
IPC分类号： H01L29/78 , H01L29/423 , H01L29/06 , H01L29/66
摘要： Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, and a gate electrode is formed over the substrate. The gate electrode has a sidewall, and the gate electrode is laterally positioned between the first source/drain region and the second source/drain region. A buffer dielectric layer is formed that includes a first dielectric layer having a first portion positioned between the substrate and the gate electrode. The dielectric layer also has a second portion positioned on the substrate laterally between the sidewall of the gate electrode and the first source/drain region. The first portion of the dielectric layer has a first thickness, and the second portion of the first dielectric layer has a second thickness that is less than the first thickness.
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公开(公告)号：US10529819B2
公开(公告)日：2020-01-07
申请号：US15803742
申请日：2017-11-04
发明人： Namchil Mun , Shiang Yang Ong , Jeoung Mo Koo , Raj Verma Purakh
IPC分类号： H01L29/66 , H01L29/872 , H01L29/06 , H01L29/40
摘要： The present invention discloses a Schottky diode. The Schottky diode comprises a substrate having a device well. A drift region is disposed within the device well. A guard ring region is disposed within the device well and adjacent to the drift region. A field isolation region and a dielectric film are disposed on a top substrate surface. The dielectric film is aligned to the field isolation region. A field plate is disposed over the field isolation region and the dielectric film. The field plate completely covers a top surface of the dielectric film and partially overlaps the guard ring region. A conductive contact layer is disposed adjacent to the dielectric film. The conductive contact layer contacts a portion of the device well to define a Schottky diode interface.
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3.发明申请公开(公告)号：US20180082997A1
公开(公告)日：2018-03-22
申请号：US15267627
申请日：2016-09-16
发明人： Ming Li , Namchil Mun , Jeoung Mo Koo , Raj Verma Purakh
IPC分类号： H01L27/06 , H01L29/78 , H01L29/40 , H01L29/10 , H01L29/06 , H01L27/092 , H01L29/66 , H01L21/8238
CPC分类号： H01L27/0617 , H01L21/8238 , H01L27/092 , H01L29/063 , H01L29/1095 , H01L29/407 , H01L29/408 , H01L29/66681 , H01L29/66734 , H01L29/7809 , H01L29/7813 , H01L29/7816
摘要： VDMOS transistors, Bipolar-CMOS-DMOS (BCD) devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices are provided. In an example, a BCD device having a VDMOS transistor includes a buried layer over a substrate and an epitaxial layer over the buried layer and having an upper surface. Deep trench isolation regions extend from the upper surface of the epitaxial layer, into the substrate, and isolate a VDMOS region from a device region. In the VDMOS region, a source region is adjacent the upper surface, a vertical gate structure extends into the epitaxial layer, a body region is located adjacent the vertical gate structure and forms a channel, and a VDMOS conductive structure extends through the epitaxial layer and into the buried layer, which is a drain for the VDMOS transistor. The VDMOS conductive structure is a drain contact to the buried layer.
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公开(公告)号：US09831304B1
公开(公告)日：2017-11-28
申请号：US15271599
申请日：2016-09-21
发明人： Mun Tat Yap , Shiang Yang Ong , Namchil Mun , Tat Wei Chua , Raj Verma Purakh , Jeoung Mo Koo
IPC分类号： H01L29/06 , H01L21/66 , H01L23/535 , H01L21/768 , H01L21/762 , H01L27/02
CPC分类号： H01L27/0207 , H01L21/76224 , H01L21/76895 , H01L23/535 , H01L23/585
摘要： Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes determining a guard ring width within an integrated circuit design layout, where a guard ring with the guard ring width surrounds an active area in the integrated circuit design layout. A deep trench location is calculated for replacing the guard ring, where the deep trench location depends on the guard ring width. The guard ring in the integrated circuit design layout is replaced with a deep trench having the deep trench location. The deep trench is formed within a substrate at the deep trench location, where the deep trench surrounds the active area.
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公开(公告)号：US09362374B2
公开(公告)日：2016-06-07
申请号：US14253878
申请日：2014-04-16
IPC分类号： H01L29/788 , H01L29/423 , H01L27/115 , G11C16/04
CPC分类号： H01L29/42324 , G11C16/0425 , H01L27/11558 , H01L29/7881 , H01L29/7883 , H01L29/7885
摘要： Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell includes a substrate, first and second wells disposed in the substrate, a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region. The memory cell further includes a control gate disposed over the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells.
摘要翻译： 提出了一种用于非易失性存储单元的简单且无成本的多时间可编程（MTP）结构的实施例。 非易失性MTP存储单元包括衬底，设置在衬底中的第一和第二阱，具有选择栅极的第一晶体管和具有彼此相邻并且布置在第二阱上并且共享扩散区域的浮置栅极的第二晶体管。 存储单元还包括设置在第一阱上的控制栅极。 控制栅极耦合到浮动栅极，并且控制和浮置栅极包括延伸穿过第一和第二阱的相同栅极层。
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6.发明授权公开(公告)号：US11955514B2
公开(公告)日：2024-04-09
申请号：US17335093
申请日：2021-06-01
发明人： Bong Woong Mun , Jeoung Mo Koo
CPC分类号： H01L29/0653 , H01L29/66681 , H01L29/7816
摘要： The embodiments herein relate to field-effect transistors (FETs) with a gate structure in a dual-depth trench isolation structure and methods of forming the same. The FET includes a substrate having an upper surface, a trench isolation structure, and a gate structure adjacent to the trench isolation structure. The trench isolation structure has a first portion having a lower surface and a second portion having a lower surface in the substrate; the lower surface of the first portion is above the lower surface of the second portion.
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公开(公告)号：US20230361173A1
公开(公告)日：2023-11-09
申请号：US18354941
申请日：2023-07-19
发明人： Bong Woong Mun , Wanbing Yi , Juan Boon Tan , Jeoung Mo Koo
IPC分类号： H01L29/06 , H01L21/762 , H01L23/528 , H01L23/14
CPC分类号： H01L29/0649 , H01L21/76224 , H01L23/528 , H01L23/147
摘要： A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
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公开(公告)号：US11791379B2
公开(公告)日：2023-10-17
申请号：US17644626
申请日：2021-12-16
发明人： Bong Woong Mun , Wanbing Yi , Juan Boon Tan , Jeoung Mo Koo
IPC分类号： H01L29/06 , H01L23/528 , H01L21/762 , H01L23/14
CPC分类号： H01L29/0649 , H01L21/76224 , H01L23/147 , H01L23/528
摘要： A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
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公开(公告)号：US11764273B2
公开(公告)日：2023-09-19
申请号：US17335091
申请日：2021-06-01
发明人： Bong Woong Mun , Jeoung Mo Koo
IPC分类号： H01L29/40
CPC分类号： H01L29/407 , H01L29/404
摘要： The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.
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公开(公告)号：US11282953B2
公开(公告)日：2022-03-22
申请号：US16847750
申请日：2020-04-14
发明人： Ming Li , Sivaramasubramaniam Ramasubramaniam , Dong Hyun Shin , Di Wu , Yunpeng Xu , Chenji Zou , Jeoung Mo Koo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/311 , H01L21/762 , H01L29/417 , H01L29/66
摘要： According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region.
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