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    THREE ELECTRODE CAPACITOR STRUCTURE USING SPACED CONDUCTIVE PILLARS
    4.
    发明申请
    THREE ELECTRODE CAPACITOR STRUCTURE USING SPACED CONDUCTIVE PILLARS 有权

    公开(公告)号：US20230123402A1

    公开(公告)日：2023-04-20

    申请号：US17451172

    申请日：2021-10-18

    申请人： GlobalFoundries Singapore Pte. Ltd.

    发明人： EeJan Khor ,  Ramasamy Chockalingam ,  Juan Boon Tan

    IPC分类号： H01L49/02

    摘要： A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

    Resistive random access memory devices
    6.
    发明授权
    Resistive random access memory devices 有权

    公开(公告)号：US11515475B2

    公开(公告)日：2022-11-29

    申请号：US15931607

    申请日：2020-05-14

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Curtis Chun-I Hsieh ,  Wei-Hui Hsu ,  Wanbing Yi ,  Yi Jiang ,  Kai Kang ,  Juan Boon Tan

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

    Memory devices and methods of forming memory devices
    8.
    发明授权
    Memory devices and methods of forming memory devices 有权

    公开(公告)号：US11081523B1

    公开(公告)日：2021-08-03

    申请号：US15931623

    申请日：2020-05-14

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Curtis Chun-I Hsieh ,  Wei-Hui Hsu ,  Yi Jiang ,  Wanbing Yi ,  Juan Boon Tan

    IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L45/00

    摘要： A memory device may be provided, including a base layer, an insulating layer, a first electrode, a switching element, a capping element and a second electrode. The insulating layer may be arranged over the base layer and may include a recess having opposing side walls. The first electrode may be arranged at least partially within the recess of the insulating layer and along the opposing side walls of the recess of the insulating layer. The switching element may be arranged at least partially within the recess of the insulating layer and along the first electrode. The capping element and the second electrode may be arranged at least partially within the recess of the insulating layer. The capping element may be arranged between the second electrode and the switching element, and a part of the second electrode may extend across the capping element to contact the switching element.