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    Integrated thin film resistor and metal-insulator-metal capacitor
    1.
    发明授权
    Integrated thin film resistor and metal-insulator-metal capacitor 有权

    公开(公告)号：US11545486B2

    公开(公告)日：2023-01-03

    申请号：US17062292

    申请日：2020-10-02

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Chengang Feng ,  Yanxia Shao ,  Yudi Setiawan ,  Handoko Linewih ,  Xuesong Rao

    IPC: H01L27/06 ,  H01L49/02

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.

    Reliable passivation layers for semiconductor devices
    2.
    发明授权
    Reliable passivation layers for semiconductor devices 有权
    可靠的半导体器件钝化层

    公开(公告)号：US09293388B2

    公开(公告)日：2016-03-22

    申请号：US14060582

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Xuesong Rao ,  Meng Meng Vanessa Chong ,  Chim Seng Seet ,  Hendro Mario ,  Aison John George ,  Chor Shu Cheng

    IPC: H01L21/4763 ,  H01L23/31 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/05599

    Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.

    Abstract translation: 公开了用于形成装置的装置和方法。 提供了用具有该器件的顶部金属层的电介质层制备的衬底。 顶级金属级包括顶级导线。 在顶部金属层上形成顶部电介质层，其包括与顶层导电线连通的顶部通孔。 在顶部介电层上形成图案化的顶部导电层。 图案化顶部导电层包括顶部通孔中的顶部通孔和顶部导电线。 形成第一钝化子层以对图案化的导电层和暴露的顶部介电层进行排列。 在第一钝化子层的表面上进行等离子体处理以形成氮化层。 形成第二钝化子层以对氮化层进行排列。 等离子体处理改善了钝化层的钝化完整性。

    Isolation for embedded devices
    4.
    发明授权
    Isolation for embedded devices 有权
    嵌入式设备的隔离

    公开(公告)号：US09349654B2

    公开(公告)日：2016-05-24

    申请号：US14228258

    申请日：2014-03-28

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Liang Li ,  Xuesong Rao ,  Martina Damayanti ,  Wei Lu ,  Alex See ,  Yoke Leng Lim

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L27/115

    CPC classification number: H01L21/823481 ,  H01L21/28229 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0649

    Abstract: Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.

    Abstract translation: 介绍了器件和形成器件的方法。 该方法包括提供用隔离区制备的底物。 衬底包括第一，第二和第三区域。 第一区域包括存储区域，第二区域包括高电压（HV）区域，第三区域包括逻辑区域。 形成覆盖基板和隔离区域的附加电介质层。 选择性地处理第一选择区域，同时保护第一非选择区域。 第一选择区域是第一，第二和第三设备区域之一。 在选择区域上形成第一栅极电介质。 第一非选择区域的顶部衬底有源面积和隔离区域在第一选择区域的处理期间不暴露并形成第一栅极电介质。

    CMP head structure
    9.
    发明授权
    CMP head structure 有权
    CMP头结构

    公开(公告)号：US09242338B2

    公开(公告)日：2016-01-26

    申请号：US14059448

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Benfu Lin ,  Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

    IPC: B24B49/16 ,  B24B37/005 ,  B24B37/32

    CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

    Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

    Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

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