公开(公告)号：US09111866B2

公开(公告)日：2015-08-18

申请号：US13788174

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yu Chen ,  Huajun Liu ,  Siow Lee Chwa ,  Soh Yun Siah ,  Yanxia Shao ,  Yoke Leng Lim

IPC: H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825

Abstract: Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

Abstract translation: 公开了一种细长分裂栅极电池的制造和所得到的器件。 实施例包括在基板上形成第一栅极，第一栅极具有上表面和覆盖上表面的硬掩模，在第一栅极和硬掩模的侧表面上形成间隔隔离层，形成第二栅极 第一栅极的一侧，第二栅极的最上部点在第一栅极的上表面下方，去除硬掩模，在暴露的垂直表面上形成间隔物，并在第一和第二栅极的暴露表面上形成硅化物 。

公开(公告)号：US12176048B2

公开(公告)日：2024-12-24

申请号：US18145341

申请日：2022-12-22

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Siow Lee Chwa ,  Handoko Linewih ,  Yudi Setiawan ,  Qiying Wong

IPC: G11C17/16 ,  G11C17/18 ,  H01C7/00 ,  H01L23/525

Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).

公开(公告)号：US10199342B2

公开(公告)日：2019-02-05

申请号：US15412067

申请日：2017-01-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xiaohua Zhan ,  Xinfu Liu ,  Yoke Leng Lim ,  Siow Lee Chwa

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L23/498 ,  H01L23/31

Abstract: A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.

公开(公告)号：US11637100B2

公开(公告)日：2023-04-25

申请号：US17400095

申请日：2021-08-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Qiying Wong ,  Handoko Linewih ,  Yudi Setiawan ,  Chengang Feng ,  Siow Lee Chwa

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L27/01

Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

公开(公告)号：US11315876B2

公开(公告)日：2022-04-26

申请号：US16792854

申请日：2020-02-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuesong Rao ,  Yun Ling Tan ,  Yudi Setiawan ,  Siow Lee Chwa

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.

公开(公告)号：US20140252445A1

公开(公告)日：2014-09-11

申请号：US13788174

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Yu Chen ,  Huajun Liu ,  Siow Lee Chwa ,  Soh Yun Siah ,  Yanxia Shao ,  Yoke Leng Lim

IPC: H01L21/283 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825

Abstract: Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

Abstract translation: 公开了一种细长分裂栅极电池的制造和所得到的器件。 实施例包括在基板上形成第一栅极，第一栅极具有上表面和覆盖上表面的硬掩模，在第一栅极和硬掩模的侧表面上形成间隔隔离层，形成第二栅极 第一栅极的一侧，第二栅极的最上部点在第一栅极的上表面下方，去除硬掩模，在暴露的垂直表面上形成间隔物，并在第一和第二栅极的暴露表面上形成硅化物 。

公开(公告)号：US20240212770A1

公开(公告)日：2024-06-27

申请号：US18145341

申请日：2022-12-22

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Siow Lee Chwa ,  Handoko Linewih ,  Yudi Setiawan ,  Qiying Wong

IPC: G11C17/16 ,  G11C17/18 ,  H01C7/00 ,  H01L23/525

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01C7/006 ,  H01L23/5256

Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).

公开(公告)号：US20240021716A1

公开(公告)日：2024-01-18

申请号：US17864499

申请日：2022-07-14

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Lawrence Selvaraj Susai ,  Handoko Linewih ,  Francois Hebert ,  Hendro Mario ,  Siow Lee Chwa

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/6656 ,  H01L29/45

Abstract: Structures including compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure comprises a layer stack on a substrate, a conductive contact extending in a vertical direction fully through the layer stack to the substrate, and a device structure including a source ohmic contact and a drain ohmic contact. The layer stack including a plurality of semiconductor layers each comprising a compound semiconductor material, the conductive contact is arranged in the layer stack to separate a first portion of the layer stack from a second portion of the layer stack, and the source ohmic contact and the drain ohmic contact have a contacting relationship with at least one of the plurality of semiconductor layers of the first portion of the layer stack.

公开(公告)号：US10475803B2

公开(公告)日：2019-11-12

申请号：US15947488

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Anson Heryanto ,  Eng Huat Toh ,  Yongshun Sun ,  Yoke Leng Lim ,  Siow Lee Chwa

IPC: H01L21/336 ,  H01L27/11524 ,  H01L21/8239 ,  H01L27/11558

Abstract: Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

公开(公告)号：US09876019B1

公开(公告)日：2018-01-23

申请号：US15209102

申请日：2016-07-13

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Xiong Zhang ,  Sunny Sadana ,  Yudi Setiawan ,  Yoke Leng Lim ,  Siow Lee Chwa

IPC: H01L21/02 ,  H01L27/11521 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/42328 ,  H01L29/66825

Abstract: Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.