公开(公告)号：US11610837B2

公开(公告)日：2023-03-21

申请号：US17027661

申请日：2020-09-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuesong Rao ,  Benfu Lin ,  Bo Li ,  Chengang Feng ,  Yudi Setiawan ,  Yun Ling Tan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.

公开(公告)号：US12176048B2

公开(公告)日：2024-12-24

申请号：US18145341

申请日：2022-12-22

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Siow Lee Chwa ,  Handoko Linewih ,  Yudi Setiawan ,  Qiying Wong

IPC: G11C17/16 ,  G11C17/18 ,  H01C7/00 ,  H01L23/525

Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).

公开(公告)号：US12224089B2

公开(公告)日：2025-02-11

申请号：US17716276

申请日：2022-04-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chuan Wang ,  Chim Seng Seet ,  Yudi Setiawan

IPC: H01C7/00 ,  H01C17/08 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a thin film resistor and methods of manufacture. A structure includes: a thin film resistor having an opening and being between an upper insulator material and a lower insulator material; and a contact extending through the opening in the thin film resistor and into the lower insulator material.

公开(公告)号：US11942415B2

公开(公告)日：2024-03-26

申请号：US17888532

申请日：2022-08-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Handoko Linewih ,  Chor Shu Cheng ,  Tze Ho Simon Chan ,  Yudi Setiawan

IPC: H01L23/522 ,  H01L21/70 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/707 ,  H01L23/5226 ,  H01L23/5228 ,  H01L28/24 ,  H01L28/40

Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

公开(公告)号：US11688785B2

公开(公告)日：2023-06-27

申请号：US16831746

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yudi Setiawan ,  Handoko Linewih

IPC: H01L29/45 ,  H01L29/16 ,  H01L21/04 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/452 ,  H01L29/7802

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate having a first surface and a second surface, the substrate comprising a wide bandgap semiconductor material. An epitaxial layer is on the first surface of the substrate and a metal germanosilicide layer is above the second surface of the substrate. The metal germanosilicide layer forms an ohmic contact to the substrate.

公开(公告)号：US11637100B2

公开(公告)日：2023-04-25

申请号：US17400095

申请日：2021-08-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Qiying Wong ,  Handoko Linewih ,  Yudi Setiawan ,  Chengang Feng ,  Siow Lee Chwa

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L27/01

Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

公开(公告)号：US11315876B2

公开(公告)日：2022-04-26

申请号：US16792854

申请日：2020-02-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuesong Rao ,  Yun Ling Tan ,  Yudi Setiawan ,  Siow Lee Chwa

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

Abstract: A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.

公开(公告)号：US11056430B1

公开(公告)日：2021-07-06

申请号：US16813835

申请日：2020-03-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chengang Feng ,  Handoko Linewih ,  Yanxia Shao ,  Yudi Setiawan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L49/02 ,  H01L23/528

Abstract: According to various embodiments, a semiconductor device may include a thin film arranged within a first inter-level dielectric layer, a masking region, and a contact plug. The masking region may be arranged over the thin film, within the first inter-level dielectric layer. The masking region may be structured to have a higher etch rate than the first inter-level dielectric layer. The contact plug may extend along a vertical axis, from a second inter-level dielectric layer to the thin film. A bottom portion of the contact plug may be surrounded by the masking region. The bottom portion of the contact plug may include a lateral member that extends along a horizontal plane at least substantially perpendicular to the vertical axis. The lateral member may be in contact with the thin film.

公开(公告)号：US20240212770A1

公开(公告)日：2024-06-27

申请号：US18145341

申请日：2022-12-22

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Siow Lee Chwa ,  Handoko Linewih ,  Yudi Setiawan ,  Qiying Wong

IPC: G11C17/16 ,  G11C17/18 ,  H01C7/00 ,  H01L23/525

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01C7/006 ,  H01L23/5256

Abstract: A one-time programmable (OTP) fuse includes a fuse link including a thin film resistor (TFR) layer between a first insulator layer and a second insulator layer. A first terminal of the OTP fuse includes a first conductive pillar through one of the first and second insulator layers and in contact with the TFR layer; and a second terminal of the OTP fuse includes a second conductive pillar through one of the first and second insulator layers and in contact with the TFR layer. The second conductive pillar and the TFR layer have a lateral contact interface having a same shape as an outer portion of the second conductive pillar. The second conductive pillar does not simply land on the TFR layer, but extends through it. Application of a current to the OTP fuse results in programming via rupture of the lateral contact interface (not electromigration in the fuse link).

公开(公告)号：US11545486B2

公开(公告)日：2023-01-03

申请号：US17062292

申请日：2020-10-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chengang Feng ,  Yanxia Shao ,  Yudi Setiawan ,  Handoko Linewih ,  Xuesong Rao

IPC: H01L27/06 ,  H01L49/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.