公开(公告)号：US11610837B2

公开(公告)日：2023-03-21

申请号：US17027661

申请日：2020-09-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuesong Rao ,  Benfu Lin ,  Bo Li ,  Chengang Feng ,  Yudi Setiawan ,  Yun Ling Tan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.

公开(公告)号：US11335635B2

公开(公告)日：2022-05-17

申请号：US16842956

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Inventor： Benfu Lin ,  Kah Wee Gan ,  Cing Gie Lim ,  Chengang Feng

IPC: H01L23/522 ,  H01L25/04

Abstract: A semiconductor device is provided. A semiconductor device includes a first and a second region, a dielectric layer, a capping layer, and a planar resistive layer. The dielectric layer is arranged over the first and second regions and the capping layer is arranged over the dielectric layer. The capping layer has a substantially planar top surface over the first and second regions. The planar resistive layer is encapsulated within the capping layer in the first device region.

公开(公告)号：US11545486B2

公开(公告)日：2023-01-03

申请号：US17062292

申请日：2020-10-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chengang Feng ,  Yanxia Shao ,  Yudi Setiawan ,  Handoko Linewih ,  Xuesong Rao

IPC: H01L27/06 ,  H01L49/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.

公开(公告)号：US11637100B2

公开(公告)日：2023-04-25

申请号：US17400095

申请日：2021-08-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Qiying Wong ,  Handoko Linewih ,  Yudi Setiawan ,  Chengang Feng ,  Siow Lee Chwa

IPC: H01L27/06 ,  H01L23/522 ,  H01L49/02 ,  H01L27/01

Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

公开(公告)号：US11056430B1

公开(公告)日：2021-07-06

申请号：US16813835

申请日：2020-03-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chengang Feng ,  Handoko Linewih ,  Yanxia Shao ,  Yudi Setiawan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L49/02 ,  H01L23/528

Abstract: According to various embodiments, a semiconductor device may include a thin film arranged within a first inter-level dielectric layer, a masking region, and a contact plug. The masking region may be arranged over the thin film, within the first inter-level dielectric layer. The masking region may be structured to have a higher etch rate than the first inter-level dielectric layer. The contact plug may extend along a vertical axis, from a second inter-level dielectric layer to the thin film. A bottom portion of the contact plug may be surrounded by the masking region. The bottom portion of the contact plug may include a lateral member that extends along a horizontal plane at least substantially perpendicular to the vertical axis. The lateral member may be in contact with the thin film.