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    Methods for fabricating integrated circuits using chemical mechanical polishing
    2.
    发明授权
    Methods for fabricating integrated circuits using chemical mechanical polishing 有权
    使用化学机械抛光制造集成电路的方法

    公开(公告)号：US09076735B2

    公开(公告)日：2015-07-07

    申请号：US14092217

    申请日：2013-11-27

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lup San Leong ,  Alan Cing Gie Lim ,  Ling Wu ,  Jian Bo Yang

    IPC: H01L21/306 ,  H01L21/02

    CPC classification number: H01L21/30625 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31053 ,  H01L21/3212 ,  H01L27/11526

    Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.

    Abstract translation: 公开了用于制造集成电路的方法。 在示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成硅材料层。 半导体衬底包括逻辑器件区域和存储器阵列区域。 存储器阵列区域具有形成在半导体衬底上的存储器件。 该方法还包括在硅材料层上并在存储器件上方形成覆盖层，并且使用第一化学机械抛光工艺在存储器阵列区域中的存储器件上方移除覆盖层，同时留下封盖的至少第一部分 层位于逻辑设备区域上。 此外，该方法包括使用第二化学机械抛光工艺从存储器阵列区域中的存储器件的上方去除第一硅材料层。

    NON-VOLATILE MEMORY ELEMENTS WITH A NARROWED ELECTRODE
    3.
    发明申请
    NON-VOLATILE MEMORY ELEMENTS WITH A NARROWED ELECTRODE 有权

    公开(公告)号：US20210320249A1

    公开(公告)日：2021-10-14

    申请号：US16846940

    申请日：2020-04-13

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lup San Leong ,  Curtis Chun-I Hsieh ,  Juan Boon Tan ,  Eng Huat Toh ,  Kin Wai Tang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.

    INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME
    5.
    发明申请
    INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME 有权
    具有改进的GAP膜电介质的集成电路及其制造方法

    公开(公告)号：US20150187641A1

    公开(公告)日：2015-07-02

    申请号：US14145581

    申请日：2013-12-31

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lei Wang ,  Lup San Leong ,  Wei Lu ,  Alex See

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

    CPC classification number: H01L21/76819 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76805 ,  H01L21/76837 ,  H01L21/76879 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.

    Abstract translation: 提供具有减少短路的集成电路和制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积覆盖半导体衬底的间隙填充电介质。 间隙填充电介质形成有具有高度差的上表面。 该方法包括减小间隙填充电介质的上表面的高度差。 此外，该方法包括沉积覆盖间隙填充电介质的层间电介质。 此外，该方法形成与覆盖半导体衬底的选定位置的电接触。

    Non-volatile memory elements with a narrowed electrode
    7.
    发明授权
    Non-volatile memory elements with a narrowed electrode 有权

    公开(公告)号：US11289649B2

    公开(公告)日：2022-03-29

    申请号：US16846940

    申请日：2020-04-13

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lup San Leong ,  Curtis Chun-I Hsieh ,  Juan Boon Tan ,  Eng Huat Toh ,  Kin Wai Tang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. A switching layer is positioned over a first electrode, and a dielectric layer is positioned over the switching layer. The dielectric layer includes an opening extending to the switching layer. A second electrode includes a portion in the opening in the dielectric layer. The portion of the second electrode is in contact with a first portion of the switching layer. The switching layer further includes a second portion positioned between the dielectric layer and the first electrode.

    Pillar contact extension and method for producing the same
    8.
    发明授权
    Pillar contact extension and method for producing the same 有权

    公开(公告)号：US10475990B2

    公开(公告)日：2019-11-12

    申请号：US15877044

    申请日：2018-01-22

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Curtis Chun-I Hsieh ,  Lup San Leong ,  Wanbing Yi ,  Cing Gie Lim ,  Yi Jiang ,  Juan Boon Tan

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

    Abstract: Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.

    METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING
    9.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS USING CHEMICAL MECHANICAL POLISHING 有权
    使用化学机械抛光制造集成电路的方法

    公开(公告)号：US20150147872A1

    公开(公告)日：2015-05-28

    申请号：US14092217

    申请日：2013-11-27

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lup San Leong ,  Alan Cing Gie Lim ,  Ling Wu ,  Jian Bo Yang

    IPC: H01L21/306 ,  H01L21/02

    CPC classification number: H01L21/30625 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31053 ,  H01L21/3212 ,  H01L27/11526

    Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The semiconductor substrate includes a logic device region and a memory array region. The memory array region has a memory device formed on the semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory device and removing the capping layer from over the memory device in the memory array region using a first chemical mechanical polishing process while leaving at least a first portion of the capping layer in place over the logic device region. Further, the method includes removing the first the silicon material layer from over the memory device in the memory array region using a second chemical mechanical polishing process.

    Abstract translation: 公开了用于制造集成电路的方法。 在示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成硅材料层。 半导体衬底包括逻辑器件区域和存储器阵列区域。 存储器阵列区域具有形成在半导体衬底上的存储器件。 该方法还包括在硅材料层上并在存储器件上方形成覆盖层，并且使用第一化学机械抛光工艺在存储器阵列区域中的存储器件上方移除覆盖层，同时留下封盖的至少第一部分 层位于逻辑设备区域上。 此外，该方法包括使用第二化学机械抛光工艺从存储器阵列区域中的存储器件的上方去除第一硅材料层。

    Memory cells and methods for forming memory cells
    10.
    发明授权
    Memory cells and methods for forming memory cells 有权

    公开(公告)号：US11641789B2

    公开(公告)日：2023-05-02

    申请号：US17355260

    申请日：2021-06-23

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Yi Jiang ,  Benfu Lin ,  Lup San Leong ,  Curtis Chun-I Hsieh ,  Wanbing Yi ,  Juan Boon Tan

    IPC: H10N70/00 ,  H01L45/00 ,  H01L27/24

    Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

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