公开(公告)号：US20240413162A1

公开(公告)日：2024-12-12

申请号：US18332147

申请日：2023-06-09

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Xuesong Rao ,  Wensheng Deng ,  Kemao Lin

IPC: H01L27/12 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a transistor including source/drain regions and a gate, the gate having a gate body. An etch stop layer is over the source/drain regions but not over the gate body. An interconnect layer is over the transistor and includes a dielectric layer. A cavity extends partially through the interconnect layer above the gate, and a portion of the dielectric layer is over the gate body and defines a bottom of the cavity. The cavity provides a mechanism to reduce both on-resistance and off-capacitance for applications such as radio frequency switches.

公开(公告)号：US20230411208A1

公开(公告)日：2023-12-21

申请号：US17807905

申请日：2022-06-21

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Wensheng Deng ,  Kemao Lin ,  Curtis Chun-I Hsieh ,  Wanbing Yi ,  Liu Xinfu ,  Rui Tze Toh ,  Yanxia Shao ,  Shucheng Yin ,  Jason Kin Wei Wong ,  Yung Fu Chong

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L23/5226 ,  H01L21/76829 ,  H01L23/53295

Abstract: Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.

公开(公告)号：US09997393B1

公开(公告)日：2018-06-12

申请号：US15616143

申请日：2017-06-07

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Yuzhan Wang ,  Bo Yu ,  Zeng Wang ,  Wensheng Deng ,  Purakh Raj Verma

IPC: H01L21/74 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76802 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes depositing an ILD layer overlying a SOI substrate including a device structure and an isolation structure. The device structure is disposed on a semiconductor layer of the SOI substrate and includes a metal silicide region and the isolation structure extends through the semiconductor layer to a buried insulator layer of the SOI substrate. A patterned mask is used for etching through the ILD layer and forming a device contact opening that exposes the metal silicide region and a substrate contact opening that exposes the isolation structure. A device contact is formed in the device contact opening. The isolation structure and the buried insulator layer are etched through to extend the substrate contact opening to a support substrate of the SOI substrate. A substrate contact is formed in the substrate contact opening.