Reliable passivation layers for semiconductor devices
    1.
    发明授权
    Reliable passivation layers for semiconductor devices 有权
    可靠的半导体器件钝化层

    公开(公告)号:US09293388B2

    公开(公告)日:2016-03-22

    申请号:US14060582

    申请日:2013-10-22

    Abstract: Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided. The top metal level includes top level conductive lines. A top dielectric layer which includes top via openings in communication with the top level conductive lines is formed over the top metal level. A patterned top conductive layer is formed on the top dielectric layer. The patterned top conductive layer includes a top via in the top via opening and a top conductive line. A first passivation sub-layer is formed to line the patterned conductive layer and exposed top dielectric layer. A plasma treatment is performed on the surface of the first passivation sub-layer to form a nitrided layer. A second passivation sub-layer is formed to line the nitrided layer. The plasma treatment improves the passivation integrity of the passivation stack.

    Abstract translation: 公开了用于形成装置的装置和方法。 提供了用具有该器件的顶部金属层的电介质层制备的衬底。 顶级金属级包括顶级导线。 在顶部金属层上形成顶部电介质层,其包括与顶层导电线连通的顶部通孔。 在顶部介电层上形成图案化的顶部导电层。 图案化顶部导电层包括顶部通孔中的顶部通孔和顶部导电线。 形成第一钝化子层以对图案化的导电层和暴露的顶部介电层进行排列。 在第一钝化子层的表面上进行等离子体处理以形成氮化层。 形成第二钝化子层以对氮化层进行排列。 等离子体处理改善了钝化层的钝化完整性。

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