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公开(公告)号：US20240070498A1
公开(公告)日：2024-02-29
申请号：US18331465
申请日：2023-06-08
Applicant: International Business Machines Corporation
Inventor： Jared Barney Hertzberg , Sami Rosenblatt , Easwar Magesan , John Aaron Smolin
CPC classification number: G06N10/00 , G06F13/4068 , H10N99/05 , B82Y10/00
Abstract: Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.
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公开(公告)号：US11734597B2
公开(公告)日：2023-08-22
申请号：US17240095
申请日：2021-04-26
Applicant: International Business Machines Corporation
Inventor： Jared Barney Hertzberg , Sami Rosenblatt , Easwar Magesan , John Aaron Smolin
CPC classification number: G06N10/00 , G06F13/4068 , H10N99/05 , B82Y10/00
Abstract: Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.
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公开(公告)号：US11908931B2
公开(公告)日：2024-02-20
申请号：US17499736
申请日：2021-10-12
Inventor： Tae Moon Roh , Hyun-Tak Kim , Sun Ae Kim
CPC classification number: H01L29/7817 , H10N99/03
Abstract: Provided is a monolithic metal-insulator transition device. The monolithic metal-insulator transition device includes a substrate including a driving region and a switching region, first and second source/drain regions on the driving region, a gate electrode between the first and second source/drain regions, an inlet well region formed adjacent to an upper surface of the substrate on the switching region, a control well region having a different conductivity type from the inlet well region between the inlet well region and a lower surface of the substrate, a first wiring electrically connecting the first source/drain region and the control well region, and a second wiring electrically connecting the second source/drain region and the inlet well region.
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公开(公告)号：US11830986B2
公开(公告)日：2023-11-28
申请号：US17010816
申请日：2020-09-02
Inventor： Min-Chuan Wang , Bo-Hsien Wu , Shang-En Liu
IPC: H01M10/38 , H01L23/58 , H01M50/20 , H01M50/502 , H10N99/00
CPC classification number: H01M10/38 , H01L23/58 , H01M50/20 , H01M50/502 , H10N99/05
Abstract: A quantum battery manufacturing method includes: providing a p-type semiconductor substrate including a first conductive substrate and a p-type semiconductor layer disposed on one surface of the first conductive substrate; providing an n-type semiconductor substrate including a second conductive substrate and an n-type semiconductor layer disposed on one surface of the second conductive substrate; and forming an electricity storage layer between the p-type semiconductor substrate and the n-type semiconductor substrate, and attaching two sides of the electricity storage layer respectively to the p-type semiconductor layer and the n-type semiconductor layer to form a quantum battery. The electricity storage layer is formed by heating a thermoplastic polymer to soften and become a liquid, mixing the liquid with energized core-shell particles, and coating a substrate with the mixture. Core-shell particles are disposed on a conductive substrate and irradiated with ultraviolet rays for energization.
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公开(公告)号：US20240415034A1
公开(公告)日：2024-12-12
申请号：US18331486
申请日：2023-06-08
Applicant: Limitless Space Institute
Inventor： Harold White
IPC: H10N99/00 , H01L31/042
Abstract: A battery includes a Casimir-effect powered cell (Casimir cell). The Casimir cell includes a first conductive wall; a second conductive wall that faces the first conductive wall; and a conductive antenna disposed in a cavity gap that is a space between the first conductive wall and the second conductive wall. The conductive antennal faces the first conductive wall and the second conductive wall. The first conductive wall and the second conductive wall produce a same first voltage potential. The conductive antenna produces a second voltage potential that is different from the first voltage potential. A voltage that is the difference between the first voltage potential and the second voltage potential is generated by Casimir phenomenon based on arrangement of the conductive antenna between the first conductive wall and the second conductive wall.
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Patent Agency Ranking
公开(公告)号：US20240196767A1
公开(公告)日：2024-06-13
申请号：US18063969
申请日：2022-12-09
Applicant: International Business Machines Corporation
Inventor： Bogdan Cezar Zota , Kirsten Emilie Moselund , Peter Mueller
IPC: H10N99/00
CPC classification number: H10N99/05
Abstract: A method for forming a semiconductor structure comprising quantum dots with self-aligned gate structures is disclosed. The method comprises structuring a doped silicon-on-isolator to build a source area, a linear structure extending from the source area having at least two distinct broadened areas, a first and a second gate structure simultaneously by a single lithography process; covering the structures with a blanket oxide layer, forming an opening in the blanket oxide layer at a lateral end of the linear structure, etching back the linear structure and the at least two distinct broadened areas below the blanket oxide until the source area is reached, and filling the hollow template with a semiconductor material different to the silicon such that the at least two broadened areas build quantum dot areas.
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公开(公告)号：US11839167B2
公开(公告)日：2023-12-05
申请号：US17134953
申请日：2020-12-28
Applicant: Microsoft Technology Licensing, LLC
Inventor： Parsa Bonderson , Chetan Nayak , David Reilly , Andrea Franchini Young , Michael Zaletel
Abstract: Apparatus, methods, and systems are disclosed for robust scalable topological quantum computing. Quantum dots are fabricated as van der Waals heterostructures, supporting localized topological phases and non-Abelian anyons (quasiparticles). Large bandgaps provide noise immunity. Three-dot structures include an intermediate quantum dot between two computational quantum dots. With the intermediate quantum dot in an OFF state, quasiparticles at the computational quantum dots can be isolated, with long lifetimes. Alternatively, the intermediate quantum dot can be controlled to decrease the quasiparticle tunneling barrier, enabling fast computing operations. A computationally universal suite of operations includes quasiparticle initialization, braiding, fusion, and readout of fused quasiparticle states, with, optionally, transport or tunable interactions—all topologically protected. Robust qubits can be operated without error correction. Quasilinear arrays of quantum dots or qubits can be scaled arbitrarily, up to resource limits, and large-scale topological quantum computers can be realized. Extensive two-dimensional arrays can also be used.
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公开(公告)号：US11690306B2
公开(公告)日：2023-06-27
申请号：US17407170
申请日：2021-08-19
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Curtis Chun-I Hsieh , Wei-Hui Hsu , Wanbing Yi , Juan Boon Tan
CPC classification number: H10N99/03
Abstract: A resistive memory device is provided. The resistive memory device comprises a first metal oxide layer above a body electrode. A correlated electron layer located between a source and a drain and above the first metal oxide layer. A gate above a bottom portion of the correlated electron layer.
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公开(公告)号：US12198008B2
公开(公告)日：2025-01-14
申请号：US18331465
申请日：2023-06-08
Applicant: International Business Machines Corporation
Inventor： Jared Barney Hertzberg , Sami Rosenblatt , Easwar Magesan , John Aaron Smolin
Abstract: Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.
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公开(公告)号：US12041864B2
公开(公告)日：2024-07-16
申请号：US17491726
申请日：2021-10-01
Applicant: Paul Scherrer Institut , UNIVERSITY OF BASEL , UNIVERSITY OF HEIDELBERG , INSTITUTUL NATIONAL DE CERCETARE-DEZVOLTARE PENTRU TEHNOLOGII IZOTOPICE SI MOLECULARE
Inventor： Thomas Jung , Aisha Ahsan , Sk Rejaul , Mehdi Heydari , Lutz H. Gade , Luiza Tania Buimaga-Iarinca , Ioan Cristian Morari
IPC: H10N99/00
CPC classification number: H10N99/05
Abstract: Surface supported quantum wells with a confined surface state capture and stably confine neutral atoms and molecules in a nanometer precise environment. Depending on the physico-chemical conditions in the capturing process, the degree of occupancy, the temperature of the solid substrate, and/or the history of external stimuli like electromagnetic field pulses, these atoms, molecules or clusters assume unique configurations. The atoms or molecules are able to remain coupled to the quantum-well specific electronic state in the confinement and as such exhibit local and delocalized quantum entanglement. The capturing potential arises from the superposition of Pauli repulsion between the captured object and the quantum well-specific confined electronic state. This occurs within on-surface atomic or supramolecular assemblies or surface supported coordination or covalent networks.
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