公开(公告)号：US09911805B2

公开(公告)日：2018-03-06

申请号：US15349100

申请日：2016-11-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

公开(公告)号：US09590059B2

公开(公告)日：2017-03-07

申请号：US14851284

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/40 ,  H01L27/06 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L29/42344 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/90 ,  H01L29/408

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material.

Abstract translation: 一些实施例涉及集成电路（IC）。 IC包括包括闪存区域和电容器区域的半导体衬底。 闪存单元布置在闪速存储器区域上，并且包括布置在闪存单元的第一和第二源/漏区之间的多晶硅选择栅极。 闪速存储器单元还包括一个控制栅极，该控制栅极与选择栅极并排设置，并通过控制栅极电介质层与选择栅极分离。 电容器布置在电容器区域上，包括：多晶硅第一电容器板和多晶硅第二电容器板，它们彼此互数位化并且通过电容器介电层彼此分离。 电容介质层和控制栅介质层由相同的材料制成。

公开(公告)号：US09570539B2

公开(公告)日：2017-02-14

申请号：US14851357

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L28/90 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1157 ,  H01L27/11573 ,  H01L28/40 ,  H01L29/517 ,  H01L29/66545

Abstract: Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.

Abstract translation: 本公开的一些实施例涉及布置在半导体衬底上的集成电路（IC），其包括闪存区域，电容器区域和逻辑区域。 电容器区域的上基板表面分别相对于闪光和逻辑区域的相应上基板表面凹陷。 一种电容器，其包括多晶硅底部电极，布置在所述多晶硅底部电极上的导电顶部电极以及分离所述底部和顶部电极的电容器电介质; 设置在电容器区域的凹陷的上基板表面上。 闪存单元设置在闪光区域的上基板表面上。 闪存单元包括具有与电容器的顶部电极的平坦化上表面共面的平坦化上表面的选择栅极。

公开(公告)号：US09276010B2

公开(公告)日：2016-03-01

申请号：US14296496

申请日：2014-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Fang-Lan Chu

IPC: H01L29/88 ,  H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

Abstract translation: 本公开涉及一种将非易失性存储器（NVM）嵌入高K金属栅（HKMG）集成电路中的结构和方法，其利用具有低多电阻和高编程/擦除速度的替代栅极技术。 在HKMG电路的更换栅极处理之后，在NVM器件的顶表面上形成的硅化物层防止接触形成期间的多晶硅损伤并且提供低栅极电阻，从而提高NVM器件的编程/擦除速度。

公开(公告)号：US20150333082A1

公开(公告)日：2015-11-19

申请号：US14296496

申请日：2014-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Fang-Lan Chu

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

Abstract translation: 本公开涉及一种将非易失性存储器（NVM）嵌入高K金属栅（HKMG）集成电路中的结构和方法，其利用具有低多电阻和高编程/擦除速度的替代栅极技术。 在HKMG电路的更换栅极处理之后，在NVM器件的顶表面上形成的硅化物层防止接触形成期间的多晶硅损伤并且提供低栅极电阻，从而提高NVM器件的编程/擦除速度。

公开(公告)号：US09129823B2

公开(公告)日：2015-09-08

申请号：US13854507

申请日：2013-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract translation: 所描述的实施例提供了用于蚀刻半导体主体上的有源区域并且外延沉积覆盖有源区域的半导体层的方法和半导体器件区域。 这些方法可以减轻或消除随后与STI科技相关的制造过程中遇到的问题。

公开(公告)号：US11551736B2

公开(公告)日：2023-01-10

申请号：US16943990

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang ,  Sheng-Chang Chen

IPC: G11C11/16 ,  H01L27/22 ,  G11C5/02 ,  H01L43/02 ,  G11C5/06 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

公开(公告)号：US11531524B2

公开(公告)日：2022-12-20

申请号：US16434345

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Chih-Hui Weng ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang ,  Chia-Hsiang Chen

IPC: G06F7/58 ,  G11C11/16

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

公开(公告)号：US11469372B2

公开(公告)日：2022-10-11

申请号：US17009887

申请日：2020-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A top electrode via couples the top electrode to an upper interconnect wire. A first line is tangent to a first outermost sidewall of the top electrode via and a second line is tangent to an opposing second outermost sidewall of the top electrode via. The first line is oriented at a first angle with respect to a horizontal plane that is parallel to an upper surface of the substrate and the second line is oriented at a second angle with respect to the horizontal plane. The second angle is less than the first angle.

公开(公告)号：US11380580B2

公开(公告)日：2022-07-05

申请号：US17007260

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huang Huang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen

IPC: H01L21/768 ,  G11C5/06 ,  H01L21/3213 ,  G11C11/16

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.