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公开(公告)号：US11531524B2
公开(公告)日：2022-12-20
申请号：US16434345
申请日：2019-06-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Chih-Hui Weng , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang , Chia-Hsiang Chen
Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.
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公开(公告)号：US20210109152A1
公开(公告)日：2021-04-15
申请号：US17126222
申请日：2020-12-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang
Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
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公开(公告)号：US10665321B2
公开(公告)日：2020-05-26
申请号：US15690303
申请日：2017-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Yu Wang , Ching-Huang Wang , Chun-Jung Lin , Tien-Wei Chiang , Meng-Chun Shih , Kuei-Hung Shen
Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.
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公开(公告)号：US11506706B2
公开(公告)日：2022-11-22
申请号：US17126222
申请日：2020-12-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang
Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
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Patent Agency Ranking
公开(公告)号：US20190066820A1
公开(公告)日：2019-02-28
申请号：US15690303
申请日：2017-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Yu Wang , Ching-Huang Wang , Chun-Jung Lin , Tien-Wei Chiang , Meng-Chun Shih , Kuei-Hung Shen
Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.
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公开(公告)号：US09335365B2
公开(公告)日：2016-05-10
申请号：US14724875
申请日：2015-05-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yen-Chieh Huang , Ching-Huang Wang , Tsung-Yi Yu
CPC classification number: G01R31/2644 , G01R31/26 , G01R31/2601 , G01R31/2642 , G11C16/0425 , G11C29/006 , G11C29/06 , G11C29/48 , G11C29/56008 , H01L22/34
Abstract: A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB.
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公开(公告)号：US11276649B2
公开(公告)日：2022-03-15
申请号：US16711152
申请日：2019-12-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Tien-Wei Chiang , Chia-Hsiang Chen , Meng-Chun Shih , Ching-Huang Wang
IPC: H01L23/552 , H05K9/00 , H01L43/02
Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.
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8.发明申请公开(公告)号：US20200097255A1
公开(公告)日：2020-03-26
申请号：US16434345
申请日：2019-06-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Chih-Hui Weng , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang , Chia-Hsiang Chen
Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.
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9.发明申请公开(公告)号：US20200096559A1
公开(公告)日：2020-03-26
申请号：US16411647
申请日：2019-05-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang
Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
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