公开(公告)号：US10262999B2

公开(公告)日：2019-04-16

申请号：US15671695

申请日：2017-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/28

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

公开(公告)号：US10002871B2

公开(公告)日：2018-06-19

申请号：US15492463

申请日：2017-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Pranita Kerber ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/8258 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

公开(公告)号：US10002798B2

公开(公告)日：2018-06-19

申请号：US15474071

申请日：2017-03-30

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7849

Abstract: A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

公开(公告)号：US20180151674A1

公开(公告)日：2018-05-31

申请号：US15884503

申请日：2018-01-31

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/207 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/265 ,  H01L29/417 ,  H01L29/205 ,  H01L21/762 ,  H01L21/306 ,  H01L29/45

CPC classification number: H01L29/205 ,  H01L21/2654 ,  H01L21/26586 ,  H01L21/30612 ,  H01L21/76224 ,  H01L29/0684 ,  H01L29/207 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/511 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7834

Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped 111-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.

公开(公告)号：US09972711B2

公开(公告)日：2018-05-15

申请号：US14729251

申请日：2015-06-03

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L21/365 ,  H01L29/06 ,  H01L29/78 ,  H01L29/201 ,  H01L29/207 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/78 ,  H01L29/20 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning a dummy gate stack above an active channel layer formed on a base. The method also includes selectively etching the active channel layer leaving a remaining active channel layer, and epitaxially growing silicon doped active channel material adjacent to the remaining active channel layer.

公开(公告)号：US09755078B2

公开(公告)日：2017-09-05

申请号：US14921384

申请日：2015-10-23

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Pranita Kerber ,  Christine Q. Ouyang ,  Alexander Reznicek

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor structure includes a first fin structure having a first strain located on a surface of a first insulator layer portion. The first fin structure includes a first doped silicon germanium alloy fin portion having a first germanium content and a silicon germanium alloy fin portion having a third germanium content. A second fin structure having a second strain is located on a surface of a second insulator layer portion. The second fin structure includes a second doped silicon germanium alloy fin portion having a second germanium content and a silicon germanium alloy fin portion having the third germanium content, wherein the first germanium content differs from the second germanium content and the third germanium content is greater than the first and second germanium contents, and wherein the first strain differs from the second strain.

公开(公告)号：US20170250263A1

公开(公告)日：2017-08-31

申请号：US15597870

申请日：2017-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pranita Kerber ,  Effendi Leobandung ,  Philip J. Oldiges

IPC: H01L29/66 ,  H01L29/08

CPC classification number: H01L29/66545 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/66628

Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

公开(公告)号：US09748114B2

公开(公告)日：2017-08-29

申请号：US14632531

申请日：2015-02-26

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Subramanian S. Iyer ,  Pranita Kerber ,  Ali Khakifirooz

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L21/265 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L29/36

CPC classification number: H01L21/486 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5384 ,  H01L29/36 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

公开(公告)号：US20170221926A1

公开(公告)日：2017-08-03

申请号：US15488613

申请日：2017-04-17

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Pranita Kerber ,  Alexander Reznicek ,  Joshua M. Rubin

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/845 ,  H01L23/485 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66795

Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.

公开(公告)号：US20170179232A1

公开(公告)日：2017-06-22

申请号：US14974182

申请日：2015-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L29/66 ,  H01L21/265

Abstract: A method for forming a semiconductor device comprising forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer adjacent to the sacrificial gate stack, forming a raised source/drain region on the first layer of the substrate adjacent to the spacer, forming a dielectric layer over the raised source/drain region, removing the sacrificial gate stack to expose the channel region of the first layer of the substrate, and implanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate.