公开(公告)号：US09761531B2

公开(公告)日：2017-09-12

申请号：US14842545

申请日：2015-09-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tatsuro Saito ,  Masayuki Kitamura ,  Atsuko Sakata ,  Makoto Wada ,  Akihiro Kajita ,  Tadashi Sakai

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L21/76861 ,  H01L21/76876 ,  H01L21/76885

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

公开(公告)号：US09761489B2

公开(公告)日：2017-09-12

申请号：US13987667

申请日：2013-08-20

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/53257 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

公开(公告)号：US20170256476A1

公开(公告)日：2017-09-07

申请号：US15443259

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon HAN ,  Dong-Sik PARK

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/5384 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

公开(公告)号：US20170250131A1

公开(公告)日：2017-08-31

申请号：US15251410

申请日：2016-08-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akira NAKAJIMA ,  Masaaki HATANO

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53266

Abstract: In one embodiment, a semiconductor device includes an insulator. The device further includes a plug provided in the insulator, the plug including a first barrier metal layer and a first conductive layer that is provided on the first barrier metal layer. The device further includes an interconnect provided outside the insulator, the interconnect being provided on the plug and the insulator and including the first barrier metal layer, the first conductive layer and a second conductive layer that is provided on the first conductive layer.

公开(公告)号：US20170243899A1

公开(公告)日：2017-08-24

申请号：US15591145

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Yuichi SATO ,  Yuji ASANO ,  Tetsunori MARUYAMA ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/485 ,  H01L23/522 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/786 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L27/1225 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

公开(公告)号：US20170236796A1

公开(公告)日：2017-08-17

申请号：US15587421

申请日：2017-05-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Shinya OSAKABE

IPC: H01L23/00 ,  H03F1/56 ,  H03F3/195 ,  H03H9/05 ,  H03F3/213

CPC classification number: H01L24/14 ,  H01L21/76885 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/11462 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/30101 ,  H01L2924/351 ,  H03F1/56 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/451 ,  H03H9/0514 ,  H03H9/059 ,  H01L2924/00

Abstract: A bump-equipped electronic component includes a circuit substrate and first and second bumps which are disposed on a principal surface of the circuit substrate and have different cross-sectional areas in a direction parallel or substantially parallel to the principal surface. One of the first and second bumps having a smaller cross-sectional area includes a height adjustment layer disposed in a direction perpendicular or substantially perpendicular to the principal surface.

公开(公告)号：US09735052B2

公开(公告)日：2017-08-15

申请号：US14880379

申请日：2015-10-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsiung Tsai ,  Carlos H. Diaz ,  Chung-Ju Lee ,  Shau-Lin Shue ,  Tien-I Bao ,  Yung-Hsu Wu ,  Hsin-Ping Chen

IPC: H01L27/108 ,  H01L23/52 ,  H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885

Abstract: A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric layer, forming a first patterned hard mask (HM) defining a first trench over the ESL, forming a second trench extending through the ESL and the dielectric layer. The second trench is adjacent the first trench. The method also includes filling in the first trench and the second trench with a first material layer, extending the first trench through the ESL and the dielectric layer while the first material layer is filled in the second trench to form an extended first trench, forming a first metal line within the extended first trench, forming a capping layer over the first metal line and removing a portion of the first metal line to form a first cut by using the ESL and the first material layer as an etch mask.

公开(公告)号：US09728504B2

公开(公告)日：2017-08-08

申请号：US14671358

申请日：2015-03-27

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Deyuan Xiao

IPC: H01L21/28 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L23/53276 ,  H01L21/288 ,  H01L21/76876 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for fabricating an interconnect structure. The method includes providing a substrate; and forming a first conductive layer; and forming a sacrificial layer on the substrate and the first conductive layer. The method also includes forming an opening exposing a surface of the first conductive layer in the sacrificial layer; and forming a catalyst layer on the exposed portion of the surface of the first conductive layer and a top surface of the sacrificial layer. Further, the method includes forming carbon nanotube bundles perpendicular to the surface of the substrate on the catalyst layer; and removing the sacrificial layer and the carbon bundles on the sacrificial layer. Further, the method also includes forming a first dielectric material layer covering top surfaces of the carbon nanotube bundles and a portion the surface of the substrate without carbon nanotubes to seal the carbon nanotube bundles in a space.

公开(公告)号：US20170221816A1

公开(公告)日：2017-08-03

申请号：US15489511

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Wen Wu ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L23/522 ,  H01L23/48 ,  H01L51/00 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/762 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53295 ,  H01L51/0017 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A via opening including an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

公开(公告)号：US09714473B2

公开(公告)日：2017-07-25

申请号：US14191061

申请日：2014-02-26

Applicant: Microfabrica Inc.

Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

IPC: C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  B33Y10/00 ,  B81C1/00 ,  B81C99/00 ,  C25D1/00 ,  C25D21/12 ,  H01L21/288 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.