公开(公告)号：US20170243784A1

公开(公告)日：2017-08-24

申请号：US15422923

申请日：2017-02-02

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/51 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L21/76837 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/456 ,  H01L29/517

Abstract: Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.

公开(公告)号：US09735107B2

公开(公告)日：2017-08-15

申请号：US15059652

申请日：2016-03-03

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Hong-Mao Lee ,  Huicheng Chang ,  Chia-Han Lai ,  Chi-Hsuan Ni ,  Cheng-Tung Lin ,  Huang-Yi Huang ,  Chi-Yuan Chen ,  Li-Ting Wang ,  Teng-Chun Tsai ,  Wei-Jung Lin

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.

公开(公告)号：US20170221760A1

公开(公告)日：2017-08-03

申请号：US15423320

申请日：2017-02-02

Applicant: Tokyo Electron Limited

Inventor： Jeffrey Smith ,  Anton J. deVilliers

IPC: H01L21/768 ,  H01L21/033

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76883

Abstract: Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.

公开(公告)号：US20170200643A1

公开(公告)日：2017-07-13

申请号：US15470038

申请日：2017-03-27

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/02164 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2221/1094

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

公开(公告)号：US20170194454A1

公开(公告)日：2017-07-06

申请号：US14988902

申请日：2016-01-06

Applicant: International Business Machines Corporation

Inventor： Nicolas L. Breil ,  Brett H. Engel ,  Michael A. Gribelyuk ,  Ahmet S. Ozcan

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L23/485 ,  H01L29/78

Abstract: A method includes forming a first silicide on a substrate after patterning a gate and spacer onto the substrate. A film is deposited over the substrate. A portion of the dielectric film is removed to expose the first silicide. A portion of the first silicide is removed to form a punch through region. A liner is deposited in the punch through region. A metal layer is deposited on the liner. The substrate is annealed to form a second silicide on the substrate.

公开(公告)号：US09698100B2

公开(公告)日：2017-07-04

申请号：US14829851

申请日：2015-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih Wei Lu ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76811 ,  H01L21/76813 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes providing a substrate having a first conductive feature in a first dielectric material layer; selectively etching the first conductive feature, thereby forming a recessed trench on the first conductive feature; forming an etch stop layer on the first dielectric material layer, on the first conductive feature and sidewalls of the recessed trench; forming a second dielectric material layer on the etch stop layer; forming an opening in the second dielectric material layer; and forming a second conductive feature in the opening of the second dielectric material layer. The second conductive feature is electrically connected with the first conductive feature.

公开(公告)号：US20170186688A1

公开(公告)日：2017-06-29

申请号：US15460976

申请日：2017-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Ravi Prakash SRIVASTAVA ,  Nicholas Robert STOKES

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/288 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09691897B2

公开(公告)日：2017-06-27

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US20170179023A1

公开(公告)日：2017-06-22

申请号：US15430667

申请日：2017-02-13

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Gregory M. Fritz ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/288

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

公开(公告)号：US09685372B2

公开(公告)日：2017-06-20

申请号：US14694524

申请日：2015-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien Ling Hwang ,  Hui-Jung Tsai ,  Yi-Wen Wu ,  Chung-Shi Liu

IPC: H01L21/768 ,  C23C14/34 ,  C25D5/02 ,  C25D7/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/7688 ,  C23C14/34 ,  C25D5/022 ,  C25D7/00 ,  H01L21/76879 ,  H01L21/76883 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/03826 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/13147 ,  H01L2224/1354 ,  H01L2224/13565 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.