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    Testing storage device power circuitry
    91.
    发明授权
    Testing storage device power circuitry 有权
    测试存储设备电源电路

    公开(公告)号：US09558848B2

    公开(公告)日：2017-01-31

    申请号：US14532646

    申请日：2014-11-04

    Applicant: Microsoft Corporation

    Inventor： Laura Marie Caulfield ,  Mark Alan Santaniello ,  J. Michael Andrewartha ,  John J. Siegler

    IPC: G06F17/50 ,  G11C29/50 ,  G01R31/3183 ,  G11C29/02 ,  G01R31/30 ,  G11C5/14 ,  G11C29/04

    CPC classification number: G11C29/50 ,  G01R31/3004 ,  G01R31/318342 ,  G11C5/14 ,  G11C29/021 ,  G11C29/10 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/5004 ,  G11C2029/5006

    Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.

    Abstract translation: 本发明扩展到用于测试存储设备电源电路的方法，系统和计算机程序产品。 存储设备控制器包括嵌入式测试程序。 响应于接收到测试命令，存储设备控制器执行测试程序。 在一个方面，测试程序发出多个不同的命令模式来测试存储设备组件（例如由NAND闪存设备的阵列共享）的共享电源电路。 测试程序识别导致最大总电流消耗的命令模式。 在另一方面，测试程序向共享的电源电路发出指定的指令模式（可能重复），以确定共享电源电路是否发生故障。

    Autorecovery after manufacturing/system integration
    92.
    发明授权
    Autorecovery after manufacturing/system integration 有权
    制造/系统集成后的自动恢复

    公开(公告)号：US09552895B2

    公开(公告)日：2017-01-24

    申请号：US14552863

    申请日：2014-11-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Francesco Falanga ,  Victor Tsai

    IPC: G11C29/00 ,  G11C29/44 ,  G11C16/34 ,  G11C29/52 ,  G11C29/38 ,  G11C29/04

    CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

    Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells. The control circuitry is further configured to perform a test of the particular data in response to a command received from an external device and perform a repair of the particular data when results of the test indicate that repair of the particular data is needed

    Abstract translation: 存储特定数据的存储器件，包含这种存储器件的系统以及测试这样的存储器件的方法。 存储器件包括包含特定数据的存储器单元的阵列，以及被配置为控制存储器单元阵列的操作的控制电路。 控制电路还被配置为响应于从外部设备接收的命令来执行特定数据的测试，并且当测试结果指示需要修复特定数据时执行特定数据的修复

    Scaleable look-up table based memory
    93.
    发明授权
    Scaleable look-up table based memory 有权
    基于可扩展查询表的内存

    公开(公告)号：US09548103B1

    公开(公告)日：2017-01-17

    申请号：US14806962

    申请日：2015-07-23

    Applicant: Altera Corporation

    Inventor： Philip Pan ,  Andy L. Lee ,  Lu Zhou ,  Aniket Kadkol

    IPC: G11C7/00 ,  G11C11/418 ,  G11C7/10 ,  G11C11/419 ,  G11C7/22 ,  G11C7/12 ,  G11C11/4094

    CPC classification number: G11C11/418 ,  G11C7/00 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4094 ,  G11C11/413 ,  G11C11/419 ,  G11C29/12 ,  G11C2029/0409 ,  G11C2029/1204 ,  G11C2029/2602

    Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

    Abstract translation: 提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。 逻辑元件包括具有专用复用器的第一和第二对数据路径。 在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。 逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。 控制信号确定存储元件是否用作CRAM或SRAM。 提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

    Method, apparatus and system for handling data error events with a memory controller
    97.
    发明授权
    Method, apparatus and system for handling data error events with a memory controller 有权
    用于使用存储器控制器处理数据错误事件的方法，装置和系统

    公开(公告)号：US09535782B2

    公开(公告)日：2017-01-03

    申请号：US14428338

    申请日：2014-04-16

    Applicant: Intel Corporation

    Inventor： Anil Agrawal ,  Satish Muthiyalu ,  Yingwen Chen ,  Meera Ganesan

    IPC: G06F11/00 ,  G06F11/07 ,  G11C29/52 ,  G06F3/06 ,  G11C29/04

    CPC classification number: G06F11/0793 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/106 ,  G11C29/52 ,  G11C2029/0409

    Abstract: Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

    Abstract translation: 用于为包括一个或多个备用存储器段的存储器的平台提供错误检测和校正的技术和机制。 在一个实施例中，存储器控制器执行包括对多个当前活动存储器段中的错误的检测的第一擦除操作。 对一个或多个存储器段执行附加的巡检擦除，同时存储器段可用作激活作为替换存储器段。 在另一个实施例中，如果基于活动段擦除检测到不可校正的错误事件，则发信号通知第一处理程序进程（但不是第二处理程序进程），而如果不可校正的第二处理程序进程（但不是第一处理程序进程） 基于备用段擦除检测错误事件。 在第一个处理程序进程和第二个处理程序进程中，只有第一个处理程序进程的信号会导致平台的崩溃事件。

    HYBRID READ DISTURB COUNT MANAGEMENT
    99.
    发明申请
    HYBRID READ DISTURB COUNT MANAGEMENT 审中-公开
    混合阅读干扰计数管理

    公开(公告)号：US20160342458A1

    公开(公告)日：2016-11-24

    申请号：US15162270

    申请日：2016-05-23

    Applicant: SK Hynix Memory Solutions Inc.

    Inventor： Yu CAI ,  Fan ZHANG ,  June LEE

    IPC: G06F11/07 ,  G11C29/44 ,  G11C29/42 ,  G11C16/26

    CPC classification number: G11C29/42 ,  G11C16/26 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

    Abstract: Memory systems may include a memory including a plurality of blocks, and a controller suitable for counting, with a counter, a number of reads to a block of the plurality of blocks, updating wordline information of a plurality of wordlines in the counted block when the number of reads exceeds a block read count threshold, selecting a wordline from the plurality of wordlines, determining an error rate of a neighbor wordline to the selected wordline, and reclaiming data in the block when the error rate exceeds an error threshold.

    Abstract translation: 存储器系统可以包括包括多个块的存储器，以及适于使用计数器对多个块的块进行多个读取的计数器的控制器，当在所述多个块中更新所述计数块中的多个字线的字线信息时， 读取次数超过块读取计数阈值，从多个字线选择字线，确定相邻字线对所选字线的错误率，以及当错误率超过错误阈值时回收块中的数据。

    ULTRA HIGH CAPACITY SOLID STATE DRIVE
    100.
    发明申请
    ULTRA HIGH CAPACITY SOLID STATE DRIVE 审中-公开
    超高功率固体驱动器

    公开(公告)号：US20160306768A1

    公开(公告)日：2016-10-20

    申请号：US15195912

    申请日：2016-06-28

    Applicant: NXGN DATA, INC.

    Inventor： Richard Mataya

    IPC: G06F13/40 ,  G11C29/04 ,  G11C16/26 ,  G06F13/42 ,  G11C16/10

    CPC classification number: G06F13/4068 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0032 ,  G06F2213/0036 ,  G06F2213/0042 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/765 ,  G11C2029/0401 ,  G11C2029/0409 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A solid state drive with modular memory. The solid state drive may include a modular array of memory cards installed on a controller board, each memory card being connected to the controller board utilizing a respective connector. Redundant data, e.g., parity data, may be stored in the solid state drive, making it possible for a solid state drive controller on the controller board to restore the contents of a removed memory card (e.g., a memory card that has failed) on a replacement memory card installed in its place. The connector utilized to connect each memory card to the controller board may be an industry standard, commercial off the shelf connector, e.g., an M.2 connector; the functions of the conductors in the connector may be redefined, from the industry standard definitions, for the purposes of embodiments of the present invention.

    Abstract translation: 具有模块化存储器的固态驱动器。 固态驱动器可以包括安装在控制器板上的存储卡的模块阵列，每​​个存储卡利用相应的连接器连接到控制器板。 冗余数据（例如奇偶校验数据）可以存储在固态驱动器中，使得控制器板上的固态驱动器控制器可以恢复已移除的存储卡（例如，已经发生故障的存储卡）的内容 安装在其位置的替换存储卡。 用于将每个存储卡连接到控制器板的连接器可以是工业标准，商用的现成的连接器，例如M.2连接器; 为了本发明的实施例的目的，连接器中的导体的功能可以根据工业标准定义重新定义。

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