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    Integrated circuit with overdriven and underdriven pass gates
    1.
    发明授权
    Integrated circuit with overdriven and underdriven pass gates 有权

    公开(公告)号：US10121534B1

    公开(公告)日：2018-11-06

    申请号：US14974015

    申请日：2015-12-18

    申请人： Altera Corporation

    发明人： Andy L. Lee

    IPC分类号： G11C11/417

    摘要： In one embodiment, an integrated circuit includes a pass gate circuit and a memory element circuit. The pass gate circuit receives a user signal that toggles between a high voltage level and a low voltage level. The memory element circuit outputs a control signal to control the pass gate circuit. The control signal may be asserted to be greater than the high voltage level when activating the pass gate circuit or the control signal may be deasserted to be less than the low voltage level when deactivating the pass gate circuit. In addition to that, a method on how to operate the pass gate circuit is also provided.

    STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
    2.
    发明申请
    STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS 审中-公开

    公开(公告)号：US20170322775A1

    公开(公告)日：2017-11-09

    申请号：US15601779

    申请日：2017-05-22

    申请人： Altera Corporation

    发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    IPC分类号： G06F7/575 ,  H03K19/177

    CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

    摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

    Programmable integrated circuits with in-operation reconfiguration capability
    4.
    发明授权
    Programmable integrated circuits with in-operation reconfiguration capability 有权

    公开(公告)号：US09607671B1

    公开(公告)日：2017-03-28

    申请号：US15061440

    申请日：2016-03-04

    申请人： Altera Corporation

    发明人： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

    IPC分类号： G11C7/00 ,  G11C7/20 ,  G11C5/14

    CPC分类号： G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

    摘要： Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

    Integrated Circuits with Asymmetric and Stacked Transistors
    6.
    发明申请
    Integrated Circuits with Asymmetric and Stacked Transistors 审中-公开
    具有不对称和堆叠晶体管的集成电路

    公开(公告)号：US20150318029A1

    公开(公告)日：2015-11-05

    申请号：US14268183

    申请日：2014-05-02

    申请人： Altera Corporation

    发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    IPC分类号： G11C7/10 ,  G11C5/06

    CPC分类号： H01L27/1104 ,  G11C5/06 ,  G11C7/1051 ,  G11C11/412 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/82345 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659

    摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

    摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

    PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION CAPABILITY
    9.
    发明申请
    PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION CAPABILITY 审中-公开

    公开(公告)号：US20170200484A1

    公开(公告)日：2017-07-13

    申请号：US15471325

    申请日：2017-03-28

    申请人： Altera Corporation

    发明人： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

    IPC分类号： G11C7/22 ,  G11C7/20 ,  G11C5/14

    CPC分类号： G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

    摘要： Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

    Hardened programmable devices
    10.
    发明授权
    Hardened programmable devices 有权

    公开(公告)号：US09654109B2

    公开(公告)日：2017-05-16

    申请号：US14247030

    申请日：2014-04-07

    申请人： Altera Corporation

    发明人： Andy L. Lee ,  Jeffrey T. Watt

    IPC分类号： G06F17/00 ,  H03K19/173 ,  G11C5/00 ,  H01L27/02 ,  H03K19/177

    CPC分类号： H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

    摘要： Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.