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    Structures for LUT-based arithmetic in PLDs
    1.
    发明授权
    Structures for LUT-based arithmetic in PLDs 有权

    公开(公告)号：US09658830B1

    公开(公告)日：2017-05-23

    申请号：US14320499

    申请日：2014-06-30

    Applicant: Altera Corporation

    Inventor： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    IPC: G06F7/575 ,  H03K19/177

    CPC classification number: G06F7/575 ,  H03K19/177 ,  H03K19/17728

    Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

    STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
    2.
    发明申请
    STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS 审中-公开

    公开(公告)号：US20170322775A1

    公开(公告)日：2017-11-09

    申请号：US15601779

    申请日：2017-05-22

    Applicant: Altera Corporation

    Inventor： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    IPC: G06F7/575 ,  H03K19/177

    CPC classification number: G06F7/575 ,  H03K19/177 ,  H03K19/17728

    Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

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