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公开(公告)号:US09444460B1
公开(公告)日:2016-09-13
申请号:US14087493
申请日:2013-11-22
申请人: Altera Corporation
发明人: Christopher F. Lane
CPC分类号: H03K19/0016
摘要: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level during high speed operation and may provide their output signals at relatively lower voltage levels that are less than the overdrive voltage during low power operation.
摘要翻译: 集成电路提供有诸如多路复用器的电路,其可以被选择性地配置为将不同的电源电压路由到集成电路上的不同电路块。 电路块可以包含由电源电压供电的存储器元件,并且以由电源电压确定的量值提供对应的静态输出控制信号。 来自存储元件的控制信号可以被施加到电路块中的晶体管的栅极。 集成电路上的逻辑可以在给定的电源电压电平下供电。 存储器元件可以在高速运行期间相对于给定电源电压电平升高的过驱动电压电平提供其输出信号,并且可以在低功率操作期间将其输出信号提供在小于过驱动电压的相对较低的电压电平 。
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公开(公告)号:US09331062B1
公开(公告)日:2016-05-03
申请号:US14099792
申请日:2013-12-06
申请人: Altera Corporation
发明人: Christopher F. Lane , Arifur Rahman
IPC分类号: H01L23/52 , H01L27/02 , H01L21/768
CPC分类号: H01L21/76801 , H01L23/481 , H01L23/5286 , H01L23/642 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/73 , H01L27/0629 , H01L27/0694 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/06181 , H01L2224/13025 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/48091 , H01L2224/48235 , H01L2224/73257 , H01L2924/00014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: Integrated circuits with backside power delivery capabilities are provided. An integrated circuit may include a substrate having front and back surfaces, a first interconnect stack formed on the front surface, and a second interconnect stack formed on the back surface. Routing structures that carry data signals, control signals, and other user signals may be formed only in the first interconnect stack. A large majority of routing structures that carry power supply signals may be formed in the second interconnect stack. Decoupling capacitor circuitry such as deep trench capacitors may be formed in the back surface of the substrate. The integrated circuit may be mounted on a package substrate. The first interconnect stack may be coupled to the package substrate via wire bond pads, whereas the second interconnect stack may be coupled to the package substrate via an array of solder bumps.
摘要翻译: 提供具有背面功率输送功能的集成电路。 集成电路可以包括具有前表面和后表面的基板,形成在前表面上的第一互连叠层和形成在背面上的第二互连叠层。 携带数据信号,控制信号和其他用户信号的路由结构可以仅在第一互连栈中形成。 携带电源信号的绝大多数路由结构可以形成在第二互连堆栈中。 去耦电容器电路如深沟槽电容器可以形成在衬底的背面。 集成电路可以安装在封装衬底上。 第一互连堆叠可以经由引线接合焊盘耦合到封装衬底,而第二互连堆叠可以经由焊料凸块的阵列耦合到封装衬底。
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公开(公告)号:US09219483B1
公开(公告)日:2015-12-22
申请号:US14198524
申请日:2014-03-05
申请人: Altera Corporation
IPC分类号: H03K19/177 , H03K19/08
CPC分类号: H03K19/08 , G06F17/5072
摘要: An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.
摘要翻译: 公开了一种集成电路。 集成电路可以包括接口电路区域和逻辑电路区域。 接口电路区域包括将信号传入和流出集成电路的接口电路。 逻辑电路区域包括被配置为实现逻辑功能的逻辑电路。 逻辑电路区域从至少两个侧面至少三个侧面或从四个侧面围绕接口电路区域。
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公开(公告)号:US08732646B2
公开(公告)日:2014-05-20
申请号:US13847666
申请日:2013-03-20
申请人: Altera Corporation
发明人: Andy L. Lee , Cameron R. McClintock , Brian D. Johnson , Richard G. Cliff , Srinivas T. Reddy , Christopher F. Lane , Paul Leventis , Vaughn Betz , David Lewis
IPC分类号: G06F17/50 , G06F7/38 , H03K19/173
CPC分类号: H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译: 根据本发明的一个方面,通过中断LE阵列基本信号路由体系结构,在PLD的LE阵列内形成一个孔,使得留下用于IP功能块的孔。 提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。
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公开(公告)号:US09094014B2
公开(公告)日:2015-07-28
申请号:US14243641
申请日:2014-04-02
申请人: Altera Corporation
发明人: Andy L. Lee , Cameron R. McClintock , Brian D. Johnson , Richard G. Cliff , Srinivas T. Reddy , Christopher F. Lane , Paul Leventis , Vaughn Betz , David Lewis
IPC分类号: G06F17/50 , H03K19/177
CPC分类号: H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
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公开(公告)号:US20140210515A1
公开(公告)日:2014-07-31
申请号:US14243641
申请日:2014-04-02
申请人: Altera Corporation
发明人: Andy L. Lee , Cameron R. McClintock , Brian D. Johnson , Richard G. Cliff , Srinivas T. Reddy , Christopher F. Lane , Paul Leventis , Vaughn Betz , David Lewis
IPC分类号: H03K19/177
CPC分类号: H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译: 根据本发明的一个方面,通过中断LE阵列基本信号路由体系结构,在PLD的LE阵列内形成一个孔,使得留下用于IP功能块的孔。 提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。
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