公开(公告)号：US07830709B2

公开(公告)日：2010-11-09

申请号：US11709289

申请日：2007-02-21

Applicant: Jan Keller

Inventor： Jan Keller

IPC: G11C16/04

CPC classification number: G11C13/0011 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009

Abstract: A memory device comprises a plurality of memory cells, each of which comprising a first electrode, a second electrode and an active material arranged between the first electrode and the second electrode, wherein the memory cells are grouped into memory cell groups, each memory cell group defining a memory cell group area and being configured such that corresponding first electrodes are individually addressable, and corresponding second electrodes are commonly addressable via a common select device provided within the memory cell group area of the memory cell group.

Abstract translation: 存储器件包括多个存储单元，每个存储单元包括布置在第一电极和第二电极之间的第一电极，第二电极和活性材料，其中存储器单元分组成存储单元组，每个存储单元组 限定存储单元组区域并且被配置为使得相应的第一电极可单独寻址，并且相应的第二电极可以经由设置在存储单元组的存储单元组区域内的公共选择装置共同寻址。

公开(公告)号：US07811880B2

公开(公告)日：2010-10-12

申请号：US11870215

申请日：2007-10-10

Applicant: Geoffrey Wen-Tai Shuy

Inventor： Geoffrey Wen-Tai Shuy

IPC: H01L21/00

CPC classification number: G11C11/5664 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/33 ,  G11C2213/77 ,  Y10T29/41

Abstract: A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask is positioned at a second position relative to the substrate, and a second material layer is formed above the first material layer based on the pattern on the photo mask, the second material layer being offset from the first material layer so that a first sub-cell of the memory cell includes the first material layer and not the second material layer, and a second sub-cell of the memory cell includes both the first and second material layers. A second electrode is formed above the first and second material layers.

Abstract translation: 存储器件的存储单元是通过在衬底上形成第一电极，将光掩模定位在相对于衬底的第一位置，并且基于光掩模上的图案在第一电极上形成第一材料层来制造的。 光掩模位于相对于基板的第二位置，并且基于光掩模上的图案在第一材料层的上方形成第二材料层，第二材料层从第一材料层偏移，使得第一 存储单元的子单元包括第一材料层而不是第二材料层，并且存储单元的第二子单元包括第一和第二材料层。 第二电极形成在第一和第二材料层的上方。

公开(公告)号：US20100238708A1

公开(公告)日：2010-09-23

申请号：US12721007

申请日：2010-03-10

Applicant: Hiroyuki NAGASHIMA

Inventor： Hiroyuki NAGASHIMA

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/003 ,  G11C8/10 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/76

Abstract: A nonvolatile semiconductor memory device comprising: a memory cell array including memory cells each provided at individual intersection between a first wiring and a second wiring, the memory cell comprising a variable resistive element, and predetermined numbers of the memory cells shearing the same first wiring to configure a page; a first control circuit configured to select a page subjected to data-writing, and to supply a constant voltage to the first wiring belonging to the selected page; a writing-voltage generating circuit configured to generate plural kinds of writing voltages for programming a resistance of the variable resistive element to one of three or more values based on a write-in data specifying three or more values; and a second control circuit configured to select the page subjected to data-writing, and to supply the writing voltages to predetermined numbers of the respective second wirings belonging to the selected page.

Abstract translation: 一种非易失性半导体存储器件，包括：存储单元阵列，包括各自设置在第一布线和第二布线之间的各个交点处的存储单元，所述存储单元包括可变电阻元件，以及预定数量的将相同的第一布线剪切的存储单元 配置页面 第一控制电路，被配置为选择经过数据写入的页面，并向属于所选择的页面的第一布线提供恒定电压; 写入电压产生电路，被配置为基于指定三个或更多个值的写入数据，生成用于将可变电阻元件的电阻编程为三个或更多个值中的一个的多种写入电压; 以及第二控制电路，被配置为选择经过数据写入的页面，并将写入电压提供给属于所选择的页面的各个第二布线的预定数量。

公开(公告)号：US20100238703A1

公开(公告)日：2010-09-23

申请号：US12563739

申请日：2009-09-21

Applicant: Kohichi KUBO ,  Hirofumi Inoue ,  Mitsuru Sato ,  Chikayoshi Kamata ,  Shinya Aoki ,  Noriko Bota

Inventor： Kohichi KUBO ,  Hirofumi Inoue ,  Mitsuru Sato ,  Chikayoshi Kamata ,  Shinya Aoki ,  Noriko Bota

IPC: G11C11/56 ,  H01L45/00

CPC classification number: G11C13/0007 ,  B82Y10/00 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/17 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

Abstract: An information recording/reproducing device includes a first electrode layer, a second electrode layer, a recording layer as a variable resistance between the first and second electrode layer, and a circuit which supplies a voltage to the recording layer to change a resistance of the recording layer. Each of the first and second electrode layers is comprised of IV or III-V semiconductor doped with p-type carrier or n-type carrier.

Abstract translation: 信息记录/再现装置包括第一电极层，第二电极层，作为第一和第二电极层之间的可变电阻的记录层和向记录层提供电压以改变记录电阻的电路 层。 第一和第二电极层中的每一个由掺杂有p型载体或n型载流子的IV或III-V半导体构成。

公开(公告)号：US07800934B2

公开(公告)日：2010-09-21

申请号：US11819077

申请日：2007-06-25

Applicant: Tanmay Kumar ,  S. Brad Herner ,  Christopher J. Petti

Inventor： Tanmay Kumar ,  S. Brad Herner ,  Christopher J. Petti

IPC: G11C11/00 ,  G11C11/36

CPC classification number: G11C13/00 ,  G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/009 ,  G11C2213/33 ,  H01L27/101

Abstract: A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.

Abstract translation: 一种操作非易失性存储单元的方法包括提供非易失性存储单元，该非易失性存储单元包括以第一电阻率，未编程状态制造的二极管，以及将正向偏压施加到具有大于将二极管编程所需的最小电压的二极管的幅度 将二极管切换到第二电阻率，编程状态。 第二电阻率状态低于第一电阻率状态。

公开(公告)号：US07796426B2

公开(公告)日：2010-09-14

申请号：US12090375

申请日：2005-10-17

Applicant: Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

Inventor： Osamu Tonomura ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.

Abstract translation: 一种能够提高设定操作速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。

公开(公告)号：US07791935B2

公开(公告)日：2010-09-07

申请号：US12146587

申请日：2008-06-26

Applicant: Hee Bok Kang ,  Suk Kyoung Hong

Inventor： Hee Bok Kang ,  Suk Kyoung Hong

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/008 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72

Abstract: A phase change memory device includes a phase change resistor configured to sense a change in crystallization state due to current flow in order to store data that corresponds to the crystallization state. The phase change memory device is driven by reading cell data of a selected unit cell using a reference current. The cell data is compared to write data and then it is determined whether the write data is set data or reset data if the cell data is different from the write data. The set or reset state is written to the cell and verified during a write and verification operation under various conditions to stably write the data.

Abstract translation: 相变存储器件包括相位改变电阻器，其被配置为感测由于电流流动导致的结晶状态的变化，以便存储对应于结晶状态的数据。 通过使用参考电流读取所选择的单位单元的单元数据来驱动相变存储器件。 将单元数据与写数据进行比较，然后如果单元数据与写数据不同，则确定写数据是设置数据还是复位数据。 在各种条件下的写入和验证操作期间将设置或复位状态写入单元并进行验证，以稳定地写入数据。

公开(公告)号：US07778062B2

公开(公告)日：2010-08-17

申请号：US11761400

申请日：2007-06-12

Applicant: Haruki Toda ,  Koichi Kubo

Inventor： Haruki Toda ,  Koichi Kubo

IPC: G11C11/00

CPC classification number: G11C13/0011 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0042 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

Abstract: A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.

Abstract translation: 一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值 与选择状态一样高; 以及形成在半导体基板上的用于数据读写的单元阵列下面的读/写电路，其中可变电阻元件包括由包含至少两种类型的阳离子元素的复合化合物组成的记录层，至少一种 阳离子元素是具有“d”轨道的过渡元素，其中电子未完全填充，相邻阳离子元素之间的最短距离为0.32nm以下。

公开(公告)号：US07778061B2

公开(公告)日：2010-08-17

申请号：US11582208

申请日：2006-10-16

Applicant: Warren Robinett ,  Philip J. Kuekes

Inventor： Warren Robinett ,  Philip J. Kuekes

IPC: G11C11/00

CPC classification number: G11C13/02 ,  B82Y10/00 ,  G06F11/1008 ,  G06F11/1076 ,  G11C11/54 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/009 ,  G11C2213/16 ,  G11C2213/77 ,  G11C2213/81

Abstract: Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

Abstract translation: 本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。 在本发明的一个实施例中，交叉开关存储器系统包括微米级信号线的第一层，微米级信号线的第二层，被配置为使得每个第一层纳米线与每个第一层微米信号线重叠的第一纳米线层， 以及第二层纳米线，其被配置为使得每个第二层纳米线与每个第二层微米信号线重叠并且与每个第一层纳米线重叠。 交叉开关存储器系统包括非线性隧道电阻器，其被配置为选择性地将第一层纳米线连接到第一层微型信号线并且选择性地将第二层纳米线连接到第二层微量信号线。 交叉开关存储器系统还包括非线性隧道迟滞电阻器，其被配置为在每个交叉点交叉处将每个第一层纳米线连接到每个第二层纳米线。

公开(公告)号：US07768823B2

公开(公告)日：2010-08-03

申请号：US12146522

申请日：2008-06-26

Applicant: Hee Bok Kang ,  Suk Kyoung Hong

Inventor： Hee Bok Kang ,  Suk Kyoung Hong

IPC: G11C7/00

CPC classification number: G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/008 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2207/2263 ,  G11C2213/72

Abstract: A phase change memory device and operation is described where the phase change memory device includes a phase change resistance cell storing data corresponding to a sensed crystallization state. The phase change memory device operates by reading data of a selected phase change resistance cell when in a write mode. The data to be written is compared to the read data. If the read data is different from the data to be written, it is determined whether the data to be written is a first data. An operation writing and verifying the first data in the cell under a first operating condition when the is data to be written is the first data is then performed. After performing verification, if the read data is different from the first data, the first data is written and verified in the selected phase change resistance cell under a second operating condition.

Abstract translation: 描述了相变存储器件和操作，其中相变存储器件包括存储对应于感测结晶状态的数据的相变电阻单元。 当写入模式时，相变存储器件通过读取所选择的相变电阻单元的数据来操作。 要写入的数据与读取的数据进行比较。 如果读取数据与要写入的数据不同，则确定要写入的数据是否是第一数据。 然后执行当要写入的数据是第一数据时在第一操作条件下对单元中的第一数据进行写入和验证的操作。 在执行验证之后，如果读取数据与第一数据不同，则在第二操作条件下，在所选择的相变电阻单元中写入并验证第一数据。