公开(公告)号：US20140028347A1

公开(公告)日：2014-01-30

申请号：US13561978

申请日：2012-07-30

申请人： Warren Robinett ,  R. Stanley Williams

发明人： Warren Robinett ,  R. Stanley Williams

IPC分类号： H03K19/173

CPC分类号： H03K19/173 ,  G11C13/0007 ,  H03K19/17712 ,  H03K19/17728

摘要： Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

摘要翻译： 使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。 至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。 至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态 。

公开(公告)号：US07741204B2

公开(公告)日：2010-06-22

申请号：US11590492

申请日：2006-10-30

申请人： Zhiyong Li ,  Warren Robinett

发明人： Zhiyong Li ,  Warren Robinett

IPC分类号： H01L21/44

CPC分类号： G11C5/06 ,  B82B1/00 ,  B82B3/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C5/12 ,  G11C2213/81 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L51/0595 ,  Y10S977/762 ,  Y10S977/94

摘要： Certain embodiments of the present invention are directed to a method of fabricating a mixed-scale electronic interface. A substrate is provided with a first set of conductive elements. A first layer of nanowires may be formed over the first set of conductive elements. A number of channels may be formed, with each of the channels extending diagonally through a number of the nanowires of the first layer. A number of pads may be formed, each of which is electrically interconnected with an underlying conductive element of the first set of conductive elements and one or more adjacent nanowires of the first layer of nanowires. The pads and corresponding electrically interconnected nanowires define a number of pad-interconnected-nanowire-units. Additional embodiments are directed to a method of forming a nanoimprinting mold and a method of selectively programming nanowire-to-conductive element electrical connections.

摘要翻译： 本发明的某些实施例涉及一种制造混合比例电子接口的方法。 衬底设置有第一组导电元件。 可以在第一组导电元件上形成第一层纳米线。 可以形成多个通道，其中每个通道对角地延伸穿过第一层的多个纳米线。 可以形成多个焊盘，每个焊盘与第一组导电元件的下面的导电元件和第一纳米线层的一个或多个相邻的纳米线电互连。 焊盘和相应的电互连纳米线限定了多个衬垫互连的纳米线单元。 另外的实施例涉及形成纳米压印模具的方法和选择性地编程纳米线至导电元件电连接的方法。

公开(公告)号：US07319416B2

公开(公告)日：2008-01-15

申请号：US11343325

申请日：2006-01-30

申请人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

发明人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

IPC分类号： H03M7/14

CPC分类号： G11C8/10 ,  G11C13/0023 ,  H03M13/51

摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.

摘要翻译： 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位， 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联， 代码字内部地址。

公开(公告)号：US08253443B2

公开(公告)日：2012-08-28

申请号：US12912647

申请日：2010-10-26

申请人： Warren Robinett

发明人： Warren Robinett

IPC分类号： H03K19/00 ,  H01L25/00 ,  H01L21/82 ,  H01L21/3205

CPC分类号： H01L27/2481 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/146

摘要： An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided.

摘要翻译： 用于多层电路的互连架构包括插入在多层电路中的地址引线和每个条之间的金属 - 绝缘体转换通道。 外部可变传感器在绝缘和导通状态之间选择性地转移金属 - 绝缘体通道，以选择性地连接和断开条和地址引线。 还提供了一种用于访问多层交叉电路内的可编程交叉点设备的方法。

公开(公告)号：US20120098566A1

公开(公告)日：2012-04-26

申请号：US12912647

申请日：2010-10-26

申请人： Warren Robinett

发明人： Warren Robinett

IPC分类号： H03K19/177 ,  H01L47/00

CPC分类号： H01L27/2481 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/146

摘要： An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided.

摘要翻译： 用于多层电路的互连架构包括插入在多层电路中的地址引线和每个条之间的金属 - 绝缘体转换通道。 外部可变传感器在绝缘和导通状态之间选择性地转移金属 - 绝缘体通道，以选择性地连接和断开条和地址引线。 还提供了一种用于访问多层交叉电路内的可编程交叉点设备的方法。

公开(公告)号：US07778061B2

公开(公告)日：2010-08-17

申请号：US11582208

申请日：2006-10-16

申请人： Warren Robinett ,  Philip J. Kuekes

发明人： Warren Robinett ,  Philip J. Kuekes

IPC分类号： G11C11/00

CPC分类号： G11C13/02 ,  B82Y10/00 ,  G06F11/1008 ,  G06F11/1076 ,  G11C11/54 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/009 ,  G11C2213/16 ,  G11C2213/77 ,  G11C2213/81

摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

摘要翻译： 本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。 在本发明的一个实施例中，交叉开关存储器系统包括微米级信号线的第一层，微米级信号线的第二层，被配置为使得每个第一层纳米线与每个第一层微米信号线重叠的第一纳米线层， 以及第二层纳米线，其被配置为使得每个第二层纳米线与每个第二层微米信号线重叠并且与每个第一层纳米线重叠。 交叉开关存储器系统包括非线性隧道电阻器，其被配置为选择性地将第一层纳米线连接到第一层微型信号线并且选择性地将第二层纳米线连接到第二层微量信号线。 交叉开关存储器系统还包括非线性隧道迟滞电阻器，其被配置为在每个交叉点交叉处将每个第一层纳米线连接到每个第二层纳米线。

公开(公告)号：US20100094580A1

公开(公告)日：2010-04-15

申请号：US12288021

申请日：2008-10-15

申请人： Joseph Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

发明人： Joseph Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC分类号： G01R31/00

CPC分类号： G01R31/317

摘要： Embodiments of the present invention are directed to cost-effective defect amelioration in manufactured electronic devices that include nanoscale components. Certain embodiments of the present invention are directed to amelioration of defects in electronic devices that contain nanoscale demultiplexers. In certain embodiments of the present invention, the nanoscale-demultiplexer-containing devices include reconfigurable encoders. In one embodiment of the present invention, the table of codes within a reconfigurable encoder is permuted, and a device is configured in accordance with the permuted codes, in order to produce a permuted table of codes that, when input to an appropriately configured nanoscale demultiplexer, produces correct outputs despite defects in the nanoscale demultiplexer.

摘要翻译： 本发明的实施例涉及在包括纳米级组件的制造的电子设备中的经济有效的缺陷改善。 本发明的某些实施例涉及改善包含纳米级解复用器的电子设备中的缺陷。 在本发明的某些实施例中，含纳米级解复用器的装置包括可重构编码器。 在本发明的一个实施例中，可重构编码器内的代码表被置换，并且根据置换代码配置器件，以便产生置换的代码表，当输入到适当配置的纳米级解复用器 ，尽管纳米级解复用器中存在缺陷，但仍能产生正确的输出。

公开(公告)号：US08773882B2

公开(公告)日：2014-07-08

申请号：US12761300

申请日：2010-04-15

申请人： Zhiyong Li ,  Warren Robinett

发明人： Zhiyong Li ,  Warren Robinett

IPC分类号： G11C5/06 ,  G11C5/12 ,  B82Y10/00 ,  B82B1/00 ,  B82B3/00 ,  B82Y40/00

CPC分类号： G11C5/06 ,  B82B1/00 ,  B82B3/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C5/12 ,  G11C2213/81 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L51/0595 ,  Y10S977/762 ,  Y10S977/94

摘要： Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state. Other embodiments of the present invention are directed to a nanowire structure including a mixed-scale interface.

摘要翻译： 本发明的某些实施例涉及一种编程纳米线至导电元件电连接的方法。 该方法包括：提供包括覆盖有第一纳米线层的多个导电元件的衬底，至少一些导电元件通过单独的开关结与多于一个的纳米线电耦合，每个开关结配置在 低电导状态或高电导状态; 以及将所述开关结的一部分从所述低电导状态切换到所述高电导状态或所述高电导状态至所述低电导状态，使得所述第一纳米线层的单个纳米线电耦合到不同的导电元件 使用在高电导状态下配置的不同的一个开关结的导电元件的数量。 本发明的其它实施方案涉及包括混合规模界面的纳米线结构。

公开(公告)号：US08121807B2

公开(公告)日：2012-02-21

申请号：US12288021

申请日：2008-10-15

申请人： Joseph Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

发明人： Joseph Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC分类号： G01R27/28

CPC分类号： G01R31/317

摘要： Embodiments of the present invention are directed to cost-effective defect amelioration in manufactured electronic devices that include nanoscale components. Certain embodiments of the present invention are directed to amelioration of defects in electronic devices that contain nanoscale demultiplexers. In certain embodiments of the present invention, the nanoscale-demultiplexer-containing devices include reconfigurable encoders. In one embodiment of the present invention, the table of codes within a reconfigurable encoder is permuted, and a device is configured in accordance with the permuted codes, in order to produce a permuted table of codes that, when input to an appropriately configured nanoscale demultiplexer, produces correct outputs despite defects in the nanoscale demultiplexer.

摘要翻译： 本发明的实施例涉及在包括纳米级组件的制造的电子设备中的经济有效的缺陷改善。 本发明的某些实施例涉及改善包含纳米级解复用器的电子设备中的缺陷。 在本发明的某些实施例中，含纳米级解复用器的装置包括可重构编码器。 在本发明的一个实施例中，可重构编码器内的代码表被置换，并且根据置换代码配置器件，以便产生置换的代码表，当输入到适当配置的纳米级解复用器 ，尽管纳米级解复用器中存在缺陷，但仍能产生正确的输出。

公开(公告)号：US08112700B2

公开(公告)日：2012-02-07

申请号：US12011175

申请日：2008-01-23

申请人： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

发明人： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

IPC分类号： G11C29/00

CPC分类号： G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

摘要： One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

摘要翻译： 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，采用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，均匀分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。