-
公开(公告)号：US09300434B2
公开(公告)日：2016-03-29
申请号：US14125292
申请日：2012-06-08
Applicant: Erik S. Daniel , Robert W. Techentin
Inventor： Erik S. Daniel , Robert W. Techentin
CPC classification number: H04L1/004 , G06F11/10 , G06F13/423 , H03M13/51 , H04L1/0042 , H04L25/14 , H04L25/4908
Abstract: Zero sum signaling schemes utilize coding across data words to allow the use of single-ended buffers while mitigating simultaneous switching noise (SSN) in digital systems. Zero sum signaling may include balanced zero sum coding (target disparity=0) and nearly balanced zero sum coding (target disparity=±d). Zero sum signaling may reduce simultaneous switching noise as compared to single-ended signaling while allowing a reduction in the number of physical channels (e.g. circuit board traces) by nearly a factor of two as compared to differential signaling.
Abstract translation: 零和信令方案利用跨数据字的编码，以允许使用单端缓冲器，同时减轻数字系统中的同时开关噪声（SSN）。 零和信号可以包括平衡零和编码（目标差异= 0）和几乎平衡的零和编码（目标差异=±d）。 与单端信号相比，零和信号可以减少同时的开关噪声，同时允许与差分信号相比将物理信道（例如电路板迹线）的数量减少近一倍。
-
公开(公告)号：US08812939B2
公开(公告)日：2014-08-19
申请号：US13358203
申请日：2012-01-25
Applicant: Xueshi Yang , Gregory Burd
Inventor： Xueshi Yang , Gregory Burd
CPC classification number: G06F11/1012 , G11C2029/0411 , H03M13/1102 , H03M13/152 , H03M13/23 , H03M13/2957 , H03M13/3707 , H03M13/3738 , H03M13/41 , H03M13/51
Abstract: Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.
Abstract translation: 提供了使用包括主解码器和辅助解码器的解码器对数据进行解码的系统和方法。 从存储设备检索码字。 主解码器尝试使用与码字相关联的硬数据来解码码字。 如果主解码器失败，则解码器控制器可以接收到故障指示，该解码器控制器激活辅助解码器。 辅助解码器尝试使用与码字相关联的硬数据或软数据对码字进行解码。 主解码器被设计为消耗更少的功率，消耗更少的硅面积，并且具有比辅助解码器更高的吞吐量。 主解码器被配置为在首先尝试解码码字时，具有成功地解码存储在存储设备中的码字的概率高于故障并且要求辅助解码器解码码字。
-
3.发明授权Forward error correction (FEC) auto negotiation for an optical transport network (OTN) 有权用于光传输网络（OTN）的前向纠错（FEC）自动协商
公开(公告)号：US08433969B1
公开(公告)日：2013-04-30
申请号：US12949568
申请日：2010-11-18
Applicant: Chaoping Wu
Inventor： Chaoping Wu
CPC classification number: H04L1/0035 , H03M13/1102 , H03M13/1194 , H03M13/132 , H03M13/136 , H03M13/1505 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2957 , H03M13/353 , H03M13/3761 , H03M13/51 , H03M13/6306 , H04J2203/0057 , H04L1/0009 , H04L1/0039
Abstract: In an Optical Transport Network communication device using a plurality of forward error correction (FEC) algorithms, a method is provided for auto negotiating an FEC algorithm between network-connected devices. The first device sends an FEC auto negotiation (AN) request message to a second device. If the first device receives the FEC AN response from the second device, the first device selects the FEC algorithm suggested in the FEC AN response. In the event that the first device is unable to negotiate a mutually agreed upon FEC algorithm with the second device, the first device enters a trial-and-error mode, beginning with a first FEC algorithm. The first device iteratively cycles through each of the plurality of n FEC algorithms, and measures error statistics associated with the nth FEC algorithms. The first device compares the n sets of error statistics and selects an FEC algorithm associated with the minimum number of errors.
Abstract translation: 在使用多个前向纠错（FEC）算法的光传输网络通信设备中，提供了一种用于在网络连接的设备之间自动协商FEC算法的方法。 第一设备向第二设备发送FEC自动协商（AN）请求消息。 如果第一设备从第二设备接收到FEC AN响应，则第一设备选择在FEC AN响应中建议的FEC算法。 在第一设备不能与第二设备协商相互同意的FEC算法的情况下，第一设备从第一FEC算法开始进入试错模式。 第一设备迭代地遍历多个n个FEC算法中的每一个，并且测量与第n个FEC算法相关联的误差统计。 第一个设备比较n组错误统计信息，并选择与最小错误数相关联的FEC算法。
-
公开(公告)号：US20070055868A1
公开(公告)日：2007-03-08
申请号：US10557904
申请日：2004-05-14
Applicant: Eric Brier , Jacques Fournier , Pascal Moitrel , Olivier Benoit , Philippe Proust
Inventor： Eric Brier , Jacques Fournier , Pascal Moitrel , Olivier Benoit , Philippe Proust
IPC: G06F21/00
CPC classification number: H04L9/004 , H03M13/05 , H03M13/51 , H04L9/003 , H04L2209/125
Abstract: The invention relates to a method for secure data transmission in connections between two functional modules of an electronic unit. A first module of a message of k bits in a word code of n bits is injection coded with a constant Hamming weight of w. The word of code is transmitted to a second module. An error signal is generated when the Hamming weight of the word of code of n bits, received by the second module, is different from w. In the absence of error, the code word is decoded, where k, w and n are whole numbers. The invention further relates to a corresponding electronic circuit.
Abstract translation: 本发明涉及一种用于在电子单元的两个功能模块之间的连接中的安全数据传输的方法。 n位的字代码中的k位的消息的第一模块以恒定的汉明权重w进行注入编码。 代码字被传送到第二个模块。 当由第二模块接收到的n位的码字的汉明权重与w不同时，产生错误信号。 在没有错误的情况下，代码字被解码，其中k，w和n是整数。 本发明还涉及相应的电子电路。
-
公开(公告)号：US4176287A
公开(公告)日：1979-11-27
申请号：US896071
申请日：1978-04-13
Applicant: James J. Remedi
Inventor： James J. Remedi
Abstract: A CMOS decoder capable of providing a one of n, a two of n, or a three of n decoded output, where n is equal to the number of outputs of the decoder and is a function of the number of bits in a digital signal to be decoded. A first plurality of transistors are used to precharge each of the decoder's outputs to a first voltage potential. A second plurality of transistors are placed in series between the first node and each of the outputs. The second plurality of transistors are controlled by the coded digital signal that is being decoded. The number of decoded outputs can be varied by connecting some of the outputs to some of the transistors of the second plurality of transistors or by connecting others of the outputs to junctions formed by the series placed transistors. In a preferred embodiment, a pair of back-to-back inverters are connected to each of the outputs to provide a static decoder.
Abstract translation: 能够提供n，n中的n个或n个解码输出中的三个的CMOS解码器，其中n等于解码器的输出数，并且是数字信号中的位数的函数 被解码。 使用第一多个晶体管来将每个解码器的输出预充电到第一电压电位。 在第一节点和每个输出之间串联放置第二多个晶体管。 第二多个晶体管由被解码的编码数字信号控制。 可以通过将一些输出连接到第二多个晶体管的一些晶体管或通过将其他输出连接到由串联放置的晶体管形成的结而改变解码输出的数量。 在优选实施例中，一对背对背反相器连接到每个输出以提供静态解码器。
-
公开(公告)号：US4090173A
公开(公告)日：1978-05-16
申请号：US751505
申请日：1976-12-17
Applicant: Henry C. Sibley
Inventor： Henry C. Sibley
CPC classification number: G08C25/00 , G06F11/1625 , H03M13/51 , H04L1/00
Abstract: An all-digital communication system is arranged to exhibit fail-safe qualities. Each message includes a pair of words, each word separated from every other word by framing information in the form of two bits, either 1/0 or 0/1. Each word in the message is arranged to exhibit a constant ratio of 1's to 0's, so that more than a single change in any bit location is needed to change from one valid message word to another. The second word in each message is the complement of the first. Two decoders are disclosed, a hard-wired embodiment and an embodiment employing a microprocessor. In the hard-wired embodiment, straightforward decoding is employed to determine the apparent message, and the apparent message is encoded to generate a locally generated message which is then compared, bit by bit, with the received message employing vital logic techniques. Assuming each of the received and locally generated bits compare, the message is validated.In the microprocessor embodiment, decoding of each word is accomplished by a table. Several checks are run to determine that the microprocessor is operating properly. The checks if successfully completed, produce a check word, which is not stored in the machine. The check word generated by decoding of the second word of a message should be complement of the first check word. External hardware determines the existence of each check word, in sequence, and allows the decoded microprocessor output to be effective.
Abstract translation: 全数字通信系统被安排为具有故障安全性质。 每个消息包括一对单词，每个单词通过以1/0或0/1的两位形式的成帧信息与每个其他单词分离。 消息中的每个字被布置为呈现1到0的恒定比率，使得需要多于一个位置的单个改变以从一个有效的消息字改变到另一个。 每条消息中的第二个字是第一个的补语。 公开了两个解码器，硬接线实施例和采用微处理器的实施例。 在硬接线的实施例中，采用简单的解码来确定明显的消息，并且对视在的消息进行编码以产生本地产生的消息，然后将该消息逐位地与接收到的使用重要逻辑技术的消息进行比较。 假设接收到的和本地产生的比特中的每一个比较，则该消息被验证。
-
公开(公告)号：US3965457A
公开(公告)日：1976-06-22
申请号：US415423
申请日：1973-11-13
Applicant: Keith Harwood
Inventor： Keith Harwood
IPC: G05B19/05 , H03M13/51 , H04J3/12 , H04Q1/39 , H04Q1/457 , H04Q3/545 , H04Q11/04 , G06F15/46 , G05B15/02 , G05B19/02
CPC classification number: H04J3/12 , G05B19/05 , H03M13/51 , H04Q1/39 , H04Q1/4575 , H04Q11/04 , H04Q11/0407 , H04Q3/54591 , G05B2219/15055
Abstract: A digital control processor for controlling a number of relay sets from digital information received from a digital PABX. The digital control processor consists essentially of a first-in first-out memory and a combinational logic unit. The memory stores information relevant to an operation to be performed by the processor and re-cycles the information until the operation has been performed. The memory determines the action of the combinational logic unit which action includes changing the state of one of the relay sets. The action of the combinational logic unit is determined by time varying data states from the memory and/or from a relay set or sets. The digital control processor acts as an interface device between the digital/electronic world of the PABX and the analogue/mechanical world of the public exchange. The device receives digital information from a processor in the PABX and also monitors the current state of all the relay sets. The device accepts a digital signal from the PABX processor in a short time, which information relates to an action to be performed by one of the relay sets and may include information indicating a digit to be transmitted to line in the form of impulses. The device then causes the relevant relay set to perform the desired action without further reference to the PABX processor. The device is capable of locating the relay set which has been in a particular state for the longest period of time upon request from the PABX processor for a relay set in that state.
Abstract translation: 一种数字控制处理器，用于从数字PABX接收的数字信息中控制多个继电器组。 数字控制处理器主要由先入先出存储器和组合逻辑单元组成。 存储器存储与要由处理器执行的操作相关的信息，并且重新循环信息直到执行操作。 存储器确定组合逻辑单元的动作，该动作包括改变一个继电器组的状态。 组合逻辑单元的动作由来自存储器和/或来自中继集合的时变数据状态确定。 数字控制处理器充当PABX的数字/电子世界与公共交换的模拟/机械世界之间的接口设备。 该设备从PABX中的处理器接收数字信息，并监视所有继电器组的当前状态。 该设备在短时间内接收来自PABX处理器的数字信号，该信息涉及由一个继电器组执行的动作，并且可以包括指示要以脉冲形式发送到行的数字的信息。 然后，设备使相关的继电器组执行所需的动作，而无需进一步参考PABX处理器。 该设备能够根据请求从PABX处理器定位处于特定状态的中继集合，用于在该状态下的中继集。
-
公开(公告)号：US3745558A
公开(公告)日：1973-07-10
申请号：US3745558D
申请日：1972-02-28
Applicant: GTE AUTOMATIC ELECTRIC LAB INC
Inventor： MORSTADT R
Abstract: A circuit providing parallel-coded format receivers with good retention of character duration information and a high degree of immunity to channel noise, speech, and other channel energy that the receiver might detect, but which violate the parallel-code format or timing restrictions.
-
公开(公告)号：US3440493A
公开(公告)日：1969-04-22
申请号：US3440493D
申请日：1966-02-15
Applicant: BELL TELEPHONE LABOR INC
Inventor： CARON LIONEL
CPC classification number: H03M13/51
-
10.发明授权
公开(公告)号：US3310631A
公开(公告)日：1967-03-21
申请号：US28501163
申请日：1963-06-03
Applicant: ITT
Inventor： BROWN WARREN G
CPC classification number: H04J3/17 , H03M13/51 , H04J3/172 , H04M11/064
