公开(公告)号：US20130249106A1

公开(公告)日：2013-09-26

申请号：US13428439

申请日：2012-03-23

申请人： Yaojian Lin ,  Kang Chen ,  Yu Gu

发明人： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2924/00012 ,  H01L2224/03

摘要： A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

摘要翻译： 半导体器件具有半导体管芯。 围绕半导体管芯沉积密封剂。 具有导电凸块的互连结构形成在密封剂和半导体管芯上。 机械支撑层形成在互连结构上并且围绕导电凸块。 机械支撑层形成在半导体管芯的拐角上并且在互连结构的拐角上。 通过延伸到互连结构的密封剂形成开口。 导电材料沉积在开口内以形成导电的通过密封剂通过（TEV）电连接到互连结构。 将半导体器件安装到TEV并在半导体管芯上方形成封装封装（PoP）器件。 在与互连结构相对的密封剂上形成翘曲平衡层。

公开(公告)号：US20130249080A1

公开(公告)日：2013-09-26

申请号：US13426561

申请日：2012-03-21

申请人： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen

发明人： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Kang Chen

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

摘要： A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

公开(公告)号：US20130075924A1

公开(公告)日：2013-03-28

申请号：US13243558

申请日：2011-09-23

申请人： Yaojian Lin ,  Rui Huang ,  Kang Chen ,  Gu Yu

发明人： Yaojian Lin ,  Rui Huang ,  Kang Chen ,  Gu Yu

IPC分类号： H01L21/56 ,  H01L23/48 ,  H01L21/60

CPC分类号： H01L23/3128 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

摘要翻译： 半导体器件具有安装到载体上的半导体管芯。 密封剂沉积在半导体管芯和载体上。 载体被移除。 在密封剂和半导体管芯上形成第一绝缘层。 通过第一绝缘层形成第一通孔以暴露半导体管芯的接触焊盘。 第一导电层形成在第一绝缘层上并且形成在第一通孔中，以电连接到半导体管芯的接触焊盘。 在第一绝缘层和第一导电层上形成第二绝缘层。 通过激光直接消融通过第二绝缘层形成第二通孔，并与第一通孔对准或偏移以暴露第一导电层。 第二导电层形成在第二绝缘层上并进入第二通孔中。 可以通过密封剂形成导电孔。

公开(公告)号：US20120187568A1

公开(公告)日：2012-07-26

申请号：US13326157

申请日：2011-12-14

申请人： Yaojian Lin ,  Jose Alvin Caparas ,  Kang Chen ,  Hin Hwa Goh

发明人： Yaojian Lin ,  Jose Alvin Caparas ,  Kang Chen ,  Hin Hwa Goh

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73259 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

摘要： A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

摘要翻译： 半导体器件具有第一半导体管芯，其包括安装在具有热可释放层的载体上的TSV。 具有第一热膨胀系数CTE的第一密封剂沉积在第一半导体管芯上。 第一密封剂包括第一密封剂的周边中的升高部分，其减少翘曲。 暴露TSV的表面。 第二半导体管芯安装到TSV的表面，并在第一和第二半导体管芯之间形成间隙。 具有第二CTE的第二密封剂沉积在第一和第二半导体管芯上并且在间隙内。 第一个CTE大于第二个CTE。 在一个实施例中，第一和第二密封剂形成在追逐模具中。 在第一和第二半导体管芯上形成互连结构。

公开(公告)号：US20120161279A1

公开(公告)日：2012-06-28

申请号：US13311266

申请日：2011-12-05

申请人： Yaojian Lin ,  Kai Liu ,  Kang Chen

发明人： Yaojian Lin ,  Kai Liu ,  Kang Chen

IPC分类号： H01L25/00 ,  H01L21/50

CPC分类号： H01L28/10 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1206 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30107 ,  H03H2001/0078 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

摘要翻译： 半导体器件具有第一半导体管芯。 在第一半导体管芯上形成第一电感器。 第二电感器形成在第一电感器上并与第一电感器对准。 在第一半导体管芯和第一和第二电感器上形成绝缘层。 导电桥形成在绝缘层之上并电连接在第二电感器和第一半导体管芯之间。 在一个实施例中，半导体器件具有第二半导体管芯，并且在第一和第二半导体管芯之间形成导电层。 在另一实施例中，在第一半导体管芯上形成电容器。 在另一个实施例中，绝缘层在第一半导体管芯的覆盖区之上具有第一厚度，并且第二厚度小于第一半导体管芯的覆盖区之外的第一厚度。

公开(公告)号：US20110278736A1

公开(公告)日：2011-11-17

申请号：US13191318

申请日：2011-07-26

申请人： Yaojian Lin ,  Kang Chen

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L23/522 ,  H01L21/60 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/04 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/0613 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/13015 ,  H01L2224/81

摘要： A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.

摘要翻译： 半导体器件具有临时载体。 半导体管芯被定向成具有朝着临时载体并且安装到临时载体的有源表面。 密封剂在临时载体上沉积有第一表面，并且与第一表面相对的第二表面沉积在半导体管芯的背面上。 移除临时载体。 去除半导体管芯的周边中的密封剂的一部分，以在密封剂的第一表面中形成开口。 互连结构形成在半导体管芯的有源表面上并延伸到密封剂层中的开口中。 通孔形成并从密封剂的第二表面延伸到开口。 在通孔中形成第一凸起并且电连接到互连结构。

公开(公告)号：US08766426B2

公开(公告)日：2014-07-01

申请号：US12890161

申请日：2010-09-24

申请人： Hin Hwa Goh ,  Xusheng Bao ,  Yung Kuan Hsiao ,  Kang Chen ,  Rui Huang

发明人： Hin Hwa Goh ,  Xusheng Bao ,  Yung Kuan Hsiao ,  Kang Chen ,  Rui Huang

IPC分类号： H01L23/02

CPC分类号： H01L23/544 ,  H01L23/055 ,  H01L23/10 ,  H01L23/552 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/167 ,  H01L2924/1676 ,  H01L2924/3511 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供载体; 将具有部件连接器的集成电路装置安装在载体上; 在所述集成电路装置上放置约束结构，用于控制所述部件连接器与所述载体接合期间所述集成电路装置的翘曲，从而使所述部件连接器中的一些与所述载体分离; 并将所有组件连接器连接到载体上。

公开(公告)号：US08455991B2

公开(公告)日：2013-06-04

申请号：US12890338

申请日：2010-09-24

申请人： Yung Kuan Hsiao ,  Xusheng Bao ,  Kang Chen ,  Hin Hwa Goh ,  Rui Huang

发明人： Yung Kuan Hsiao ,  Xusheng Bao ,  Kang Chen ,  Hin Hwa Goh ,  Rui Huang

IPC分类号： H01L21/56

CPC分类号： H01L23/4334 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/27436 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8101 ,  H01L2224/81095 ,  H01L2224/81815 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92242 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有芯片互连的集成电路器件; 将附着层直接施加在集成电路装置上; 将装置加强件附接到具有附接层的集成电路装置; 将芯片载体附接到与集成电路器件连接的器件加强件的芯片互连件，用于控制集成电路器件的翘曲，以防止翘曲导致芯片互连在将芯片互连连接到芯片互连期间与芯片载体分离 芯片载体; 以及在芯片载体和集成电路器件之间施加底部填充物，以控制所有芯片互连件与芯片载体的连接性。

公开(公告)号：US08421212B2

公开(公告)日：2013-04-16

申请号：US12887681

申请日：2010-09-22

申请人： Kang Chen ,  Xusheng Bao ,  Rui Huang ,  Yung Kuan Hsiao ,  Hin Hwa Goh

发明人： Kang Chen ,  Xusheng Bao ,  Rui Huang ,  Yung Kuan Hsiao ,  Hin Hwa Goh

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16245 ,  H01L2224/24155 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2224/92135 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有结构底侧，结构顶侧和空腔的互连结构，所述结构底侧电连接到所述结构顶侧; 将集成电路完全安装在腔内，该集成电路具有与结构顶侧共面的有源侧; 形成部分覆盖所述互连结构和所述集成电路的封装，所述封装具有与所述结构顶侧和所述有源侧共面的封装顶侧; 在结构顶侧上形成顶部再钝化层和封装; 并将散热器安装在顶部再钝化层上，以从活动侧去除热量。

公开(公告)号：US20120074588A1

公开(公告)日：2012-03-29

申请号：US12890338

申请日：2010-09-24

申请人： Yung Kuan Hsiao ,  Xusheng Bao ,  Kang Chen ,  Hin Hwa Goh ,  Rui Huang

发明人： Yung Kuan Hsiao ,  Xusheng Bao ,  Kang Chen ,  Hin Hwa Goh ,  Rui Huang

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/4334 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/27436 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8101 ,  H01L2224/81095 ,  H01L2224/81815 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92242 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有芯片互连的集成电路器件; 将附着层直接施加在集成电路装置上; 将装置加强件附接到具有附接层的集成电路装置; 将芯片载体附接到与集成电路器件连接的器件加强件的芯片互连件，用于控制集成电路器件的翘曲，以防止翘曲导致芯片互连在将芯片互连连接到芯片互连期间与芯片载体分离 芯片载体; 以及在芯片载体和集成电路器件之间施加底部填充物，以控制所有芯片互连件与芯片载体的连接性。