公开(公告)号：US20160064238A1

公开(公告)日：2016-03-03

申请号：US14507840

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成材料层; 在所述材料层上形成图案化的第一硬掩模; 在材料上形成图案化的第二硬掩模; 利用图案化的第一硬掩模和图案化的第二硬掩模去除用于形成牺牲心轴的材料层的一部分; 形成与牺牲心轴相邻的侧壁间隔物; 去除牺牲心轴; 以及使用所述侧壁间隔件来移除所述基板的一部分。

公开(公告)号：US20160064224A1

公开(公告)日：2016-03-03

申请号：US14469606

申请日：2014-08-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Chih-Kai Hsu

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28132 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有限定在其上的第一区域和第二区域的衬底; 在所述基板上形成多个鳍状结构; 在鳍状结构上形成栅极层; 在栅极层上形成材料层; 图案化用于在第一区域中的栅极层上形成牺牲心轴的材料层; 形成与牺牲心轴相邻的侧壁间隔物; 去除牺牲心轴; 在所述第二区域上形成图案化掩模; 并且利用图案化掩模和侧壁间隔物去除栅极层的一部分。

公开(公告)号：US09159798B2

公开(公告)日：2015-10-13

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US20140361373A1

公开(公告)日：2014-12-11

申请号：US13913511

申请日：2013-06-09

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面，其中第一顶表面高于第二顶表面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US08895396B1

公开(公告)日：2014-11-25

申请号：US13940220

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Ssu-I Fu ,  Yu-Hsiang Hung ,  Cheng-Guo Chen ,  Chung-Fu Chang ,  Chien-Ting Lin

IPC: H01L21/8236 ,  H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.

Abstract translation: 外延工艺包括以下步骤。 在基板上形成第一栅极和第二栅极。 分别在第一栅极和第二栅极旁边的基板上形成两个第一间隔物。 分别在两个第一间隔物旁边的衬底中形成具有第一轮廓的两个第一外延层。 形成第二间隔材料以覆盖第一栅极和第二栅极。 蚀刻覆盖第二栅极的第二间隔物材料，以在第二栅极旁边的衬底上形成第二间隔物，并在第二间隔物旁边露出第一外延层，同时保留覆盖第一栅极的第二间隔物材料。 在第二间隔物旁边的衬底中的暴露的第一外延层由具有不同于第一轮廓的第二轮廓的第二外延层代替。

公开(公告)号：US20140273368A1

公开(公告)日：2014-09-18

申请号：US13802542

申请日：2013-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/8238

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US08829575B2

公开(公告)日：2014-09-09

申请号：US13727540

申请日：2012-12-26

Applicant: United Microelectronics Corp.

Inventor： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

Abstract translation: 半导体结构包括栅极，双间隔物和两个凹槽。 门位于基板上。 双垫片位于栅极旁边的基板上。 所述凹部位于所述基板和所述双间隔件中，其中所述凹槽旁边的所述凹部的侧壁具有下端部和上端部，并且所述下端部位于所述基板中，而所述上端部为锐角 位于双垫片中并靠近基板。 本发明还提供一种形成所述半导体结构的半导体工艺。

公开(公告)号：US11948975B2

公开(公告)日：2024-04-02

申请号：US17509061

申请日：2021-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/665

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

公开(公告)号：US20210193668A1

公开(公告)日：2021-06-24

申请号：US17194324

申请日：2021-03-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Yu-Hsiang Hung ,  Ming-Te Wei

IPC: H01L27/108

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.

公开(公告)号：US20200105764A1

公开(公告)日：2020-04-02

申请号：US16175858

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Gang-Yi Lin ,  Yu-Hsiang Hung ,  Ying-Chih Lin ,  Feng-Yi Chang ,  Ming-Te Wei ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chia-Liang Liao

IPC: H01L27/108 ,  G11C11/402 ,  H01L23/538

Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.