公开(公告)号：US20240355894A1

公开(公告)日：2024-10-24

申请号：US18757573

申请日：2024-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/0607 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US11626500B2

公开(公告)日：2023-04-11

申请号：US17369985

申请日：2021-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US10930517B2

公开(公告)日：2021-02-23

申请号：US16532477

申请日：2019-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L21/77 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

公开(公告)号：US10795255B2

公开(公告)日：2020-10-06

申请号：US16175858

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Gang-Yi Lin ,  Yu-Hsiang Hung ,  Ying-Chih Lin ,  Feng-Yi Chang ,  Ming-Te Wei ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chia-Liang Liao

IPC: G03F1/36 ,  H01L23/538 ,  G03F1/38 ,  H01L21/033 ,  H01L21/308 ,  G03F1/00 ,  G03F7/20 ,  G03F7/00 ,  H01L27/108

Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

公开(公告)号：US10418251B2

公开(公告)日：2019-09-17

申请号：US15688885

申请日：2017-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L21/8232 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

公开(公告)号：US10395991B2

公开(公告)日：2019-08-27

申请号：US15830008

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.

公开(公告)号：US09786662B1

公开(公告)日：2017-10-10

申请号：US15226906

申请日：2016-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Yu-Hsiang Hung

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate pattern is formed on the substrate, a first spacer is formed around the first gate pattern, part of the first gate pattern is removed to form a first slot, a first dielectric layer is formed into the first slot, and a replacement metal gate (RMG) process is performed to transform part of the first gate pattern into a metal gate.

公开(公告)号：US20170256459A1

公开(公告)日：2017-09-07

申请号：US15599430

申请日：2017-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L23/535 ,  H01L27/088 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/0226 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.

公开(公告)号：US09530646B2

公开(公告)日：2016-12-27

申请号：US14629491

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  An-Chi Liu ,  Chih-Wei Wu ,  Jyh-Shyang Jenq ,  Shih-Fang Hong ,  En-Chiuan Liou ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Mei-Chen Chen ,  Chia-Hsun Tseng

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/66 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L22/12

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，提供具有多个心轴图案的图案化的硬掩模层。 接下来，通过图案化的硬掩模在基板上形成多个第一心轴。 接下来，执行至少一个侧壁图像传送（SIT）处理。 最后，在基板上形成多个散热片，其中每个翅片具有预定的临界尺寸（CD），并且每个心轴图案具有比预定CD大5-8倍的CD。

公开(公告)号：US20160197162A1

公开(公告)日：2016-07-07

申请号：US15009808

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。