公开(公告)号：US20150035069A1

公开(公告)日：2015-02-05

申请号：US13954991

申请日：2013-07-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Po-Chao Tsao ,  Chung-Fu Chang ,  Cheng-Guo Chen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1211 ,  H01L21/845

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.

Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板中形成翅片状结构; 在衬底上并在鳍状结构的底部周围形成浅沟槽隔离（STI）; 在STI和鳍状结构上形成第一栅极结构; 以及去除STI的一部分以暴露在第一栅极结构下方的STI的侧壁。

公开(公告)号：US20230048684A1

公开(公告)日：2023-02-16

申请号：US17976888

申请日：2022-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Wei-Da Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Yi-Chuan Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuan-Ting Lu ,  Kuo-Yu Liao

IPC: H01L29/94 ,  H01L29/66

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

公开(公告)号：US09960083B1

公开(公告)日：2018-05-01

申请号：US15342114

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-You Chen ,  Cheng-Guo Chen ,  Kun-Yuan Wu ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo ,  Shang-Jr Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

公开(公告)号：US20150155386A1

公开(公告)日：2015-06-04

申请号：US14620209

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US20140363935A1

公开(公告)日：2014-12-11

申请号：US13912218

申请日：2013-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ssu-I Fu ,  Cheng-Guo Chen ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chien-Ting Lin

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

Abstract translation: 半导体工艺包括以下步骤。 提供基板。 至少在基板上形成翅片状结构，形成与翅片状结构部分重叠的栅极结构。 随后，在衬底上覆盖地形成电介质层，除去电介质层的一部分，以在鳍状结构上形成第一间隔物，除了鳍状结构之外还形成第二间隔物。 此外，去除第二间隔件和鳍状结构的一部分以在栅极结构的一侧形成至少一个凹部，并且在凹部中形成外延层。

公开(公告)号：US10276663B2

公开(公告)日：2019-04-30

申请号：US15213370

申请日：2016-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20180019341A1

公开(公告)日：2018-01-18

申请号：US15213370

申请日：2016-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7391 ,  H01L29/7848 ,  H01L29/785

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US09318609B2

公开(公告)日：2016-04-19

申请号：US14620209

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US09070710B2

公开(公告)日：2015-06-30

申请号：US13912218

申请日：2013-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ssu-I Fu ,  Cheng-Guo Chen ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chien-Ting Lin

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

Abstract translation: 半导体工艺包括以下步骤。 提供基板。 至少在基板上形成翅片状结构，形成与翅片状结构部分重叠的栅极结构。 随后，在衬底上覆盖地形成电介质层，除去电介质层的一部分，以在鳍状结构上形成第一间隔物，除了鳍状结构之外还形成第二间隔物。 此外，去除第二间隔件和鳍状结构的一部分以在栅极结构的一侧形成至少一个凹部，并且在凹部中形成外延层。

公开(公告)号：US20140339652A1

公开(公告)日：2014-11-20

申请号：US14449157

申请日：2014-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/51 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.

Abstract translation: 具有含氧金属栅极的半导体器件包括衬底，栅介质层和多层堆叠结构。 多层堆叠结构设置在基板上。 多层堆叠结构的至少一层包括功函数金属层。 更靠近栅介质层的多层堆叠结构的一层侧的氧的浓度小于与栅介质层相反的多层堆叠结构的一层的一侧的浓度。