公开(公告)号：US20140175527A1

公开(公告)日：2014-06-26

申请号：US13727540

申请日：2012-12-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

Abstract translation: 半导体结构包括栅极，双间隔物和两个凹槽。 门位于基板上。 双垫片位于栅极旁边的基板上。 所述凹部位于所述基板和所述双间隔件中，其中所述凹槽旁边的所述凹部的侧壁具有下端部和上端部，并且所述下端部位于所述基板中，而所述上端部为锐角 位于双垫片中并靠近基板。 本发明还提供一种形成所述半导体结构的半导体工艺。

公开(公告)号：US09502530B2

公开(公告)日：2016-11-22

申请号：US14935441

申请日：2015-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

公开(公告)号：US20140273368A1

公开(公告)日：2014-09-18

申请号：US13802542

申请日：2013-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/8238

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US08829575B2

公开(公告)日：2014-09-09

申请号：US13727540

申请日：2012-12-26

Applicant: United Microelectronics Corp.

Inventor： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

Abstract translation: 半导体结构包括栅极，双间隔物和两个凹槽。 门位于基板上。 双垫片位于栅极旁边的基板上。 所述凹部位于所述基板和所述双间隔件中，其中所述凹槽旁边的所述凹部的侧壁具有下端部和上端部，并且所述下端部位于所述基板中，而所述上端部为锐角 位于双垫片中并靠近基板。 本发明还提供一种形成所述半导体结构的半导体工艺。

公开(公告)号：US20160064521A1

公开(公告)日：2016-03-03

申请号：US14935441

申请日：2015-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/225 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US09214395B2

公开(公告)日：2015-12-15

申请号：US13802542

申请日：2013-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：提供具有第一类型半导体区域和第二类型半导体区域的衬底，在衬底上形成保形第一外延掩模层，在第一类型半导体区域的衬底中形成第一型外延层 在衬底上形成保形第二外延掩模层，在第二类型半导体区域的衬底中形成第二类型的外延层，以及去除第二外延掩模层。

公开(公告)号：US08753902B1

公开(公告)日：2014-06-17

申请号：US13802494

申请日：2013-03-13

Applicant: United Microelectronics Corp.

Inventor： Chia-Jong Liu ,  Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: G01R31/26

CPC classification number: H01L21/31116 ,  H01L21/3065 ,  H01L21/3086 ,  H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.

Abstract translation: 控制用于形成外延结构的蚀刻工艺的方法包括以下步骤。 提供了具有栅极的基板。 在栅极旁边的衬底上形成间隔物以限定外延结构的位置。 测量间隔物的厚度。 第一蚀刻工艺的蚀刻时间根据厚度设定。 执行第一蚀刻工艺以在间隔物旁边的衬底中形成凹部。 在凹部中形成外延结构。