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    METHOD FOR FORMING PATTERNS FOR SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD FOR FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
    用于形成半导体器件的图案的方法

    公开(公告)号：US20160351410A1

    公开(公告)日：2016-12-01

    申请号：US14741426

    申请日：2015-06-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Hao Fu ,  Home-Been Cheng ,  Ci-Dong Chu ,  Tsung-Yin Hsieh

    IPC: H01L21/308 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76877

    Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate is provided. The substrate includes a hard mask layer and a sacrificial layer formed thereon. A plurality of spacer patterns parallel with each other are formed on the substrate. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion the first blocking layer are formed on the substrate after forming the first blocking layer. Next, the sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers and the second blocking layer being used as etching masks to form a patterned hard mask layer on the substrate.

    Abstract translation: 用于形成半导体器件的图案的方法包括以下步骤。 提供基板。 基板包括硬掩模层和形成在其上的牺牲层。 在基板上形成有彼此平行的多个间隔图案。 在形成间隔物图案之后，在牺牲层中形成多个第一阻挡层。 在形成第一阻挡层之后，在衬底上形成多个第二阻挡层，暴露至少一部分牺牲层和至少一部分第一阻挡层。 接下来，用间隔物图案蚀刻牺牲层和硬掩模层，将第一阻挡层和第二阻挡层用作蚀刻掩模，以在基板上形成图案化的硬掩模层。

    Through Silicon Via and Method of Forming the Same
    2.
    发明申请
    Through Silicon Via and Method of Forming the Same 有权
    通过硅通孔及其形成方法

    公开(公告)号：US20130299949A1

    公开(公告)日：2013-11-14

    申请号：US13947125

    申请日：2013-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuo-Hsiung Huang ,  Chun-Mao Chiou ,  Hsin-Yu Chen ,  Yu-Han Tsai ,  Ching-Li Yang ,  Home-Been Cheng

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

    Abstract translation: 本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。 绝缘层设置在通孔开口的表面上。 阻挡层设置在绝缘层的表面上。 缓冲层设置在阻挡层的表面上。 导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。 缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

    Through silicon via structure
    3.
    发明申请
    Through silicon via structure 有权
    通过硅通孔结构

    公开(公告)号：US20150041961A1

    公开(公告)日：2015-02-12

    申请号：US14521456

    申请日：2014-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Chen ,  Home-Been Cheng ,  Yu-Han Tsai ,  Ching-Li Yang

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

    Abstract translation: 公开了一种硅通孔结构。 贯通硅通孔包括：基板; 设置在所述基板上并具有多个第一开口的第一电介质层，所述多个第一开口的底部位于比所述基板的原始表面低的位置; 设置在所述第一电介质层和所述基板上的通孔，所述通孔与所述多个第一开口全部不重叠， 第二电介质层，其在填充所述多个第一开口的同时，设置在所述多个第一开口内和所述通孔的侧壁上; 以及设置在所述通孔内的导电材料层，所述导电材料层在所述通孔的侧壁上具有所述第二电介质层，从而形成通硅通孔。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    4.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20140175527A1

    公开(公告)日：2014-06-26

    申请号：US13727540

    申请日：2012-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chung-Fu Chang ,  Yu-Hsiang Hung ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/6656 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.

    Abstract translation: 半导体结构包括栅极，双间隔物和两个凹槽。 门位于基板上。 双垫片位于栅极旁边的基板上。 所述凹部位于所述基板和所述双间隔件中，其中所述凹槽旁边的所述凹部的侧壁具有下端部和上端部，并且所述下端部位于所述基板中，而所述上端部为锐角 位于双垫片中并靠近基板。 本发明还提供一种形成所述半导体结构的半导体工艺。

    METHOD FOR FORMING PATTERNS FOR SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD FOR FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
    用于形成半导体器件的图案的方法

    公开(公告)号：US20170069529A1

    公开(公告)日：2017-03-09

    申请号：US15356677

    申请日：2016-11-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Hao Fu ,  Home-Been Cheng ,  Ci-Dong Chu ,  Tsung-Yin Hsieh

    IPC: H01L21/768 ,  H01L21/308 ,  H01L21/027

    CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76877

    Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate including a hard mask layer and a sacrificial layer is provided. A plurality of mandrel patterns are formed on the substrate. A spacer is respectively formed on sidewalls of the mandrel patterns. The mandrel patterns are removed to form a plurality of spacer patterns directly formed on the sacrificial layer. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion of the first blocking layers are formed on the substrate. The sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers, and the second blocking layers serving as etching masks to form a patterned hard mask layer on the substrate.

    Abstract translation: 用于形成半导体器件的图案的方法包括以下步骤。 提供了包括硬掩模层和牺牲层的基板。 在基板上形成多个心轴图案。 间隔件分别形成在心轴图案的侧壁上。 去除心轴图案以形成直接形成在牺牲层上的多个间隔图案。 在形成间隔物图案之后，在牺牲层中形成多个第一阻挡层。 在衬底上形成暴露至少一部分牺牲层和至少一部分第一阻挡层的多个第二阻挡层。 用间隔物图案，第一阻挡层和第二阻挡层用作蚀刻掩模来蚀刻牺牲层和硬掩模层，以在衬底上形成图案化的硬掩模层。

    Method for forming patterns for semiconductor device
    6.
    发明授权
    Method for forming patterns for semiconductor device 有权
    用于形成半导体器件的图案的方法

    公开(公告)号：US09536751B2

    公开(公告)日：2017-01-03

    申请号：US14741426

    申请日：2015-06-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Hao Fu ,  Home-Been Cheng ,  Ci-Dong Chu ,  Tsung-Yin Hsieh

    IPC: H01L21/308 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76877

    Abstract: A method for forming patterns for semiconductor device includes following steps. A substrate is provided. The substrate includes a hard mask layer and a sacrificial layer formed thereon. A plurality of spacer patterns parallel with each other are formed on the substrate. A plurality of first blocking layers are formed in the sacrificial layer after forming the spacer patterns. A plurality of second blocking layers exposing at least a portion of the sacrificial layer and at least a portion the first blocking layer are formed on the substrate after forming the first blocking layer. Next, the sacrificial layer and the hard mask layer are etched with the spacer patterns, the first blocking layers and the second blocking layer being used as etching masks to form a patterned hard mask layer on the substrate.

    Abstract translation: 用于形成半导体器件的图案的方法包括以下步骤。 提供基板。 基板包括硬掩模层和形成在其上的牺牲层。 在基板上形成有彼此平行的多个间隔图案。 在形成间隔物图案之后，在牺牲层中形成多个第一阻挡层。 在形成第一阻挡层之后，在衬底上形成多个第二阻挡层，暴露至少一部分牺牲层和至少一部分第一阻挡层。 接下来，用间隔物图案蚀刻牺牲层和硬掩模层，将第一阻挡层和第二阻挡层用作蚀刻掩模，以在基板上形成图案化的硬掩模层。

    Through silicon via and method of forming the same
    9.
    发明授权
    Through silicon via and method of forming the same 有权
    通过硅通孔及其形成方法

    公开(公告)号：US08841755B2

    公开(公告)日：2014-09-23

    申请号：US13947125

    申请日：2013-07-22

    Applicant: United Microelectronics Corp.

    Inventor： Kuo-Hsiung Huang ,  Chun-Mao Chiou ,  Hsin-Yu Chen ,  Yu-Han Tsai ,  Ching-Li Yang ,  Home-Been Cheng

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/525

    CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

    Abstract translation: 本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。 绝缘层设置在通孔开口的表面上。 阻挡层设置在绝缘层的表面上。 缓冲层设置在阻挡层的表面上。 导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。 缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。

    Method of controlling etching process for forming epitaxial structure
    10.
    发明授权
    Method of controlling etching process for forming epitaxial structure 有权
    控制用于形成外延结构的蚀刻工艺的方法

    公开(公告)号：US08753902B1

    公开(公告)日：2014-06-17

    申请号：US13802494

    申请日：2013-03-13

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Jong Liu ,  Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Pei-Yu Chou ,  Home-Been Cheng

    IPC: G01R31/26

    CPC classification number: H01L21/31116 ,  H01L21/3065 ,  H01L21/3086 ,  H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.

    Abstract translation: 控制用于形成外延结构的蚀刻工艺的方法包括以下步骤。 提供了具有栅极的基板。 在栅极旁边的衬底上形成间隔物以限定外延结构的位置。 测量间隔物的厚度。 第一蚀刻工艺的蚀刻时间根据厚度设定。 执行第一蚀刻工艺以在间隔物旁边的衬底中形成凹部。 在凹部中形成外延结构。

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