公开(公告)号：US09978594B1

公开(公告)日：2018-05-22

申请号：US15352118

申请日：2016-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Yen Lin ,  Ching-Yu Chang ,  Kuei-Shun Chen ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/09 ,  G03F7/004 ,  G03F7/16 ,  G03F7/038 ,  G03F7/20 ,  G03F7/32

CPC classification number: H01L21/0273 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/0382 ,  G03F7/091 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/322 ,  G03F7/325 ,  H01L21/02203 ,  H01L21/0332 ,  H01L21/266 ,  H01L21/3081 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.

公开(公告)号：US20150147826A1

公开(公告)日：2015-05-28

申请号：US14091630

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weibo Yu ,  Wen-Yu Ku ,  Kuo-Sheng Chuang ,  Chin-Hsiang Lin

IPC: H01L21/66 ,  G01N21/21 ,  H01L21/677 ,  H01L21/02 ,  H01L21/306 ,  G01B11/06 ,  H01L21/67

CPC classification number: H01L21/30604 ,  G01B11/0641 ,  G01N2201/025 ,  G01N2201/061 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/20

Abstract: An integrated system operation method is disclosed that includes the following steps: the film of a substrate is measured by a metrology apparatus to obtain a film information. The substrate is moved from the metrology apparatus to a process apparatus adjacent to the transfer apparatus. The film information is sent to the process apparatus. A film treatment is applied to the substrate in accordance with the film information.

Abstract translation: 公开了一种集成系统操作方法，其包括以下步骤：通过计量装置测量基板的膜以获得胶片信息。 基板从计量装置移动到与传送装置相邻的处理装置。 电影信息被发送到处理装置。 根据胶片信息对基材进行胶片处理。

公开(公告)号：US12292684B2

公开(公告)日：2025-05-06

申请号：US17247301

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Tzu-Yang Lin ,  Ya-Ching Chang ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/11 ,  G03F7/075 ,  G03F7/16 ,  G03F7/20 ,  H01L21/02 ,  H01L21/027 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.

公开(公告)号：US12080779B2

公开(公告)日：2024-09-03

申请号：US17408985

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Teng-Chun Tsai ,  Huang-Lin Chao ,  Akira Mineji

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66515 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

公开(公告)号：US20240045327A1

公开(公告)日：2024-02-08

申请号：US18446702

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/004 ,  G03F7/32

CPC classification number: G03F7/0042 ,  G03F7/325 ,  G03F7/0047 ,  G03F7/32 ,  G03F7/30

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.

公开(公告)号：US11852966B2

公开(公告)日：2023-12-26

申请号：US17340991

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Chien-Cheng Chen ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Pei-Cheng Hsu ,  Yih-Chen Su ,  Gaston Lee ,  Tran-Hui Shen

IPC: G03F1/24 ,  G03F1/54 ,  G03F7/20 ,  G03F1/38 ,  G03F1/22

CPC classification number: G03F1/24 ,  G03F1/38 ,  G03F1/54 ,  G03F7/2004 ,  G03F1/22

Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.

公开(公告)号：US20220382156A1

公开(公告)日：2022-12-01

申请号：US17816004

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han Lai ,  Chin-Hsiang Lin ,  Chien-Wei Wang

IPC: G03F7/039 ,  C07D247/02 ,  G03F7/004

Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.

公开(公告)号：US11411113B2

公开(公告)日：2022-08-09

申请号：US16927082

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/8238

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US11387104B2

公开(公告)日：2022-07-12

申请号：US16889506

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L21/027 ,  G03F7/40

Abstract: A method for lithography patterning includes forming an opening in a first layer over a substrate and coating a grafting solution over the first layer and filling in the opening. The grafting solution comprises a grafting compound and a solvent. The grafting compound comprises a grafting unit chemically bonded to a linking unit chemically bonded to a polymer backbone. The grafting unit is attachable to the first layer. The method further includes curing the grafting solution so that a first portion of the grafting compound is attached to a surface of the first layer, thereby forming a second layer over the surface of the first layer. The method further includes transferring a pattern including the first layer and the second layer to the substrate.

公开(公告)号：US11342193B2

公开(公告)日：2022-05-24

申请号：US17034043

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Ken-Hsien Hsieh ,  Chin-Hsiang Lin

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.