公开(公告)号：US12292684B2

公开(公告)日：2025-05-06

申请号：US17247301

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Tzu-Yang Lin ,  Ya-Ching Chang ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/11 ,  G03F7/075 ,  G03F7/16 ,  G03F7/20 ,  H01L21/02 ,  H01L21/027 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.

公开(公告)号：US11769678B2

公开(公告)日：2023-09-26

申请号：US17100218

申请日：2020-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang Lin ,  Cheng-Han Wu ,  Chen-Yu Liu ,  Kuo-Shu Tseng ,  Shang-Sheng Li ,  Chen Yi Hsu ,  Yu-Cheng Chang

IPC: H01L21/67

CPC classification number: H01L21/67242 ,  H01L21/67023

Abstract: A lithography includes a storage tank that stores process chemical fluid, an anti-collision frame, and an integrated sensor assembly. The storage tank includes a dispensing port positioned at a lowest part of the storage tank in a gravity direction. The anti-collision frame is coupled to the storage tank. An integrated sensor assembly is disposed on at least one of the anti-collision frame and the storage tank to measure a variation in fluid quality in response to fluid quality measurement of fluid.

公开(公告)号：US20180341177A1

公开(公告)日：2018-11-29

申请号：US15694222

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Wei-Han Lai ,  Tzu-Yang Lin ,  Ming-Hui Weng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32

CPC classification number: G03F7/325 ,  G03F7/038 ,  G03F7/16 ,  G03F7/20 ,  G03F7/2004

Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.

公开(公告)号：US11532499B2

公开(公告)日：2022-12-20

申请号：US17182782

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US11143963B2

公开(公告)日：2021-10-12

申请号：US16719835

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Wei-Han Lai ,  Tzu-Yang Lin ,  Ming-Hui Weng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32 ,  G03F7/16 ,  G03F7/20

Abstract: The present disclosure provides NTD developers and corresponding lithography techniques that can overcome resolution, line edge roughness (LER), and sensitivity (RLS) tradeoff barriers particular to extreme ultraviolet (EUV) technologies, thereby achieving high patterning fidelity for advanced technology nodes. An exemplary lithography method includes forming a negative tone resist layer over a workpiece; exposing the negative tone resist layer to EUV radiation; and removing an unexposed portion of the negative tone resist layer in a negative tone developer, thereby forming a patterned negative tone resist layer. The negative tone developer includes an organic solvent having a log P value greater than 1.82. The organic solvent is an ester acetate derivative represented by R1COOR2. R1 and R2 are hydrocarbon chains having four or less carbon atoms. In some implementations, R1, R2, or both R1 and R2 are propyl functional groups, such as n-propyl, isopropyl, or 2-methylpropyl.

公开(公告)号：US10859915B2

公开(公告)日：2020-12-08

申请号：US16137742

申请日：2018-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Liu ,  Tzu-Yang Lin ,  Ya-Ching Chang ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/11 ,  G03F7/20 ,  G03F7/075 ,  H01L21/027 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  G03F7/16 ,  H01L29/78

Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.

公开(公告)号：US10950485B2

公开(公告)日：2021-03-16

申请号：US16559089

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US10515847B2

公开(公告)日：2019-12-24

申请号：US16007648

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang Lin ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

公开(公告)号：US12255091B2

公开(公告)日：2025-03-18

申请号：US18516703

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/66 ,  H01L21/67 ,  H01L21/677 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US11854860B2

公开(公告)日：2023-12-26

申请号：US18055784

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/677 ,  H01L21/66 ,  H05F1/00

CPC classification number: H01L21/68757 ,  H01L21/6719 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67242 ,  H01L21/67742 ,  H01L22/10 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.