公开(公告)号：US11195737B2

公开(公告)日：2021-12-07

申请号：US16577259

申请日：2019-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Sung Kuo ,  Jhih-Yuan Yang ,  Po-Wei Chen ,  Fang-yu Liu ,  Ping-Cheng Ko ,  Chung-Cheng Chen

IPC: H01L21/673

Abstract: An apparatus for storing and transporting semiconductor elements includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pin holder integrally extending from the first rear side wall. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pivotal pin structure integrally coupled with and extending from the second rear side wall. The at least one pivotal pin structure comprises a shaft, and a head connected with the shaft. The at least one pin holder defines a cavity sized and shaped to accept the head of the at least one pivotal pin structure. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

公开(公告)号：US11532499B2

公开(公告)日：2022-12-20

申请号：US17182782

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US10964569B2

公开(公告)日：2021-03-30

申请号：US16448467

申请日：2019-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Cheng Ko ,  Tzu-Chong Tsai ,  Jhih-Yuan Yang ,  Fang-yu Liu

IPC: H01L21/673 ,  B29C45/73 ,  B29C45/74 ,  B29L31/00 ,  B29K69/00

Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

公开(公告)号：US10950485B2

公开(公告)日：2021-03-16

申请号：US16559089

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/677 ,  H01L21/67 ,  H05F1/00 ,  H01L21/66

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US12255091B2

公开(公告)日：2025-03-18

申请号：US18516703

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/66 ,  H01L21/67 ,  H01L21/677 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US11881421B2

公开(公告)日：2024-01-23

申请号：US17216247

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Tsai ,  Ping-Cheng Ko ,  Fang-yu Liu ,  Jhih-Yuan Yang

IPC: H01L21/673 ,  B29C45/72 ,  B29C45/73 ,  B29C45/74 ,  B29C45/78 ,  B29C35/16 ,  B29L31/00 ,  B29K69/00

CPC classification number: H01L21/67386 ,  B29C45/7207 ,  B29C45/73 ,  B29C45/74 ,  B29C45/78 ,  H01L21/67366 ,  H01L21/67369 ,  H01L21/67373 ,  H01L21/67396 ,  B29C2035/1616 ,  B29C2945/76531 ,  B29C2945/76668 ,  B29C2945/76688 ,  B29C2945/76765 ,  B29K2069/00 ,  B29L2031/712

Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

公开(公告)号：US11854860B2

公开(公告)日：2023-12-26

申请号：US18055784

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao Hung ,  Ping-Cheng Ko ,  Tzu-Yang Lin ,  Fang-Yu Liu ,  Cheng-Han Wu

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/677 ,  H01L21/66 ,  H05F1/00

CPC classification number: H01L21/68757 ,  H01L21/6719 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67242 ,  H01L21/67742 ,  H01L22/10 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.