公开(公告)号：US08969201B2

公开(公告)日：2015-03-03

申请号：US14469394

申请日：2014-08-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/285 ,  H01L21/60 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66636 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 在开口的侧壁和底部上的半导体层; 半导体层上的介电层; 以及填充介电层的开口的金属层。

公开(公告)号：US08932921B2

公开(公告)日：2015-01-13

申请号：US14174689

申请日：2014-02-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/4958

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

Abstract translation: 本发明提供集成电路。 集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。 第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。 第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

公开(公告)号：US08823065B2

公开(公告)日：2014-09-02

申请号：US13672258

申请日：2012-11-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Ding-Kang Shih ,  Chin-Hsiang Lin ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/417 ,  H01L29/43 ,  H01L29/45

CPC classification number: H01L29/66636 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7378 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 在开口的侧壁和底部上的半导体层; 半导体层上的介电层; 以及填充介电层的开口的金属层。

公开(公告)号：US08759173B2

公开(公告)日：2014-06-24

申请号：US14030518

申请日：2013-09-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Hsi Yeh ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01L21/336

CPC classification number: H01L29/66818 ,  H01L29/66795

Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

Abstract translation: 用于形成例如鳍状结构的半导体材料，特别是III-V材料可能在化学机械抛光步骤期间遭受结构损坏。 可以通过氧化材料损坏的表面，然后蚀刻掉氧化的材料来减少或消除这种损伤。 蚀刻步骤可以与蚀刻回图案化氧化物层（例如浅沟槽隔离层）的步骤同时完成。

公开(公告)号：US20140154848A1

公开(公告)日：2014-06-05

申请号：US14174689

申请日：2014-02-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/4958

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

Abstract translation: 本发明提供集成电路。 集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。 第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。 第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

公开(公告)号：US12148653B2

公开(公告)日：2024-11-19

申请号：US17316555

申请日：2021-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ru-Gun Liu ,  Chin-Hsiang Lin ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Yung-Sung Yen

IPC: H01L21/76 ,  H01L21/768 ,  H01L27/12

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

公开(公告)号：US12009210B2

公开(公告)日：2024-06-11

申请号：US18132843

申请日：2023-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： An-Ren Zi ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/67

CPC classification number: H01L21/0274 ,  H01L21/67115

Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.

公开(公告)号：US11966162B2

公开(公告)日：2024-04-23

申请号：US18200510

申请日：2023-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Yang Lin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/039 ,  G03F7/004 ,  G03F7/038 ,  G03F7/20 ,  G03F7/30 ,  G03F7/32 ,  G03F7/36 ,  G03F7/38 ,  G03F7/40 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: G03F7/0397 ,  G03F7/0042 ,  G03F7/0045 ,  G03F7/0382 ,  G03F7/0392 ,  G03F7/2004 ,  G03F7/30 ,  G03F7/32 ,  G03F7/36 ,  G03F7/38 ,  G03F7/40 ,  B82Y30/00 ,  B82Y40/00

Abstract: A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from:




The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is a linking group.

公开(公告)号：US20240105500A1

公开(公告)日：2024-03-28

申请号：US18106680

申请日：2023-02-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kenichi Sano ,  Chin-Hsiang Lin ,  Hsu-Kai Chang ,  Pinyen Lin

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/76229 ,  H01L21/76883 ,  H01L21/823878 ,  H01L27/088

Abstract: The present disclosure provides a method for repairing a seam within a conformally deposited material. One or more seam repairing precursor sources may be delivered to seams or voids using a carrier at a super critical fluid phase. At the super critical fluid phase, the carrier has liquid like density and gas like high diffusion capability, therefore capable of delivering the repairing precursor sources to seams or voids under surfaces of a structure. In some embodiments, carbon dioxide or argon may be used as a carrier.

公开(公告)号：US11862465B2

公开(公告)日：2024-01-02

申请号：US17589315

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

CPC classification number: H01L21/0338 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.