公开(公告)号：US20180063710A1

公开(公告)日：2018-03-01

申请号：US15249715

申请日：2016-08-29

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Li-Wen Hung ,  Jui-Hsin Lai ,  Ko-Tao Lee

IPC: H04W12/06 ,  G06F21/36 ,  G06F21/35

CPC classification number: H04W12/06 ,  G06F21/35 ,  G06F21/36 ,  G06F21/43 ,  G06F21/44 ,  H04W12/04

Abstract: Wireless communication is established between electronic devices by an initiating device transmitting a wireless communication request to a peripheral device; the initiating device detecting a visible electromagnetic pattern displayed on the peripheral device in response to the wireless communication request; the initiating device decoding the visible electromagnetic pattern to generate a passcode; and the initiating device echoing the passcode to the peripheral device to authenticate the wireless communication request without user intervention.

公开(公告)号：US20170169591A1

公开(公告)日：2017-06-15

申请号：US14966693

申请日：2015-12-11

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Pei-Yun S. Hsueh ,  Jui-Hsin Lai ,  Yinglong Xia

IPC: G06T11/20

CPC classification number: G06T11/206 ,  A61B5/00 ,  A61B5/0022 ,  A61B5/02055 ,  A61B5/021 ,  A61B5/024 ,  A61B5/04012 ,  A61B5/14542 ,  A61B5/7221 ,  A61B5/7246 ,  A61B5/7264 ,  A61B5/746 ,  A61B2503/12 ,  A61B2505/07

Abstract: One or more biological signals are obtained. The one or more biological signals are converted to one or more graph structures. Correlation between two or more of the biological signals are determined using the one or more graph structures. One or more changes in the one or more graph structures within a time window are recorded. A signal graph model is generated based on the recorded changes.

公开(公告)号：US09653441B1

公开(公告)日：2017-05-16

申请号：US15187087

申请日：2016-06-20

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Li-Wen Hung ,  Jui-Hsin Lai ,  Ko-Tao Lee

IPC: H01L33/00 ,  H01L25/16 ,  H01L29/06 ,  H01L29/04 ,  H01L29/20 ,  H01L33/32 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H01L25/00 ,  H01L27/15

CPC classification number: H01L25/167 ,  H01L25/50 ,  H01L27/15 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78681 ,  H01L33/32

Abstract: After forming an opening extending through a (100) silicon layer and a buried insulator layer and into a (111) silicon layer of a semiconductor-on-insulator (SOI) substrate, a light-emitting element is formed within the opening. A portion of the (111) silicon layer located beneath the light-emitting element is patterned to form a patterned structure for tuning light emission characteristics and enhancing efficiency of the light-emitting element. Next, at least one field effect transistor (FET) is formed on the (100) silicon layer for driving the light-emitting element.

公开(公告)号：US09647062B2

公开(公告)日：2017-05-09

申请号：US14805669

申请日：2015-07-22

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita

IPC: H01L21/8242 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/306 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L21/308

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02186 ,  H01L21/28079 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31056 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.

公开(公告)号：US20170033193A1

公开(公告)日：2017-02-02

申请号：US15248002

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/51 ,  H01L21/311 ,  H01L29/167 ,  H01L29/49 ,  H01L29/08 ,  H01L21/768

CPC classification number: H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US09437445B1

公开(公告)日：2016-09-06

申请号：US14630072

申请日：2015-02-24

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Miaomiao Wang ,  Tenko Yamashita

IPC: H01L21/308 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7855

Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

Abstract translation: 提供了一种用于形成半导体器件的技术。 牺牲心轴形成在半导体层上的硬掩模层上。 垫片形成在牺牲心轴的侧壁上。 去除牺牲心轴以留下间隔物。 掩蔽过程使第一组间隔物暴露出第二组保护。 响应于掩蔽过程，第一鳍蚀刻工艺通过第一组间隔件在半导体层中形成第一组散热片。 第一组翅片具有垂直的侧壁轮廓。 另一掩蔽工艺使第二组间隔件与第一组间隔件露出，第一组散热片被保护。 响应于另一掩蔽工艺，第二鳍蚀刻工艺使用第二组间隔件在半导体层中形成第二组散热片。 第二组翅片具有梯形侧壁轮廓。

公开(公告)号：US20160020335A1

公开(公告)日：2016-01-21

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/808 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20150364544A1

公开(公告)日：2015-12-17

申请号：US14805669

申请日：2015-07-22

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02186 ,  H01L21/28079 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31056 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure

公开(公告)号：US20150364543A1

公开(公告)日：2015-12-17

申请号：US14301587

申请日：2014-06-11

Applicant: International Business Machines Corporation

Inventor： Chia-Yu Chen ,  Zuoguang Liu ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/49 ,  H01L21/28 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02186 ,  H01L21/28079 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31056 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure

Abstract translation: 提供了半导体器件的技术。 技术涉及通过以下方式形成半导体器件：在衬底中形成翅片结构，在鳍结构的上部形成保护层，保护层相对于鳍结构的材料具有蚀刻选择性，并执行 底切蚀刻，以便在保护层下方去除翅片结构的下部，从而从翅片结构限定纳米线结构