公开(公告)号：US20130084704A1

公开(公告)日：2013-04-04

申请号：US13424811

申请日：2012-03-20

申请人： Kei WATANABE ,  Ichiro MIZUSHIMA

发明人： Kei WATANABE ,  Ichiro MIZUSHIMA

IPC分类号： H01L21/311

CPC分类号： B81C1/00492 ,  B81C2201/0149 ,  B81C2201/0198 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

摘要： According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film.

摘要翻译： 根据一个实施例，微结构的制造方法包括在图案形成材料上形成引导膜，形成固化膜，形成掩模部件，并使用掩模部件作为掩模进行图案形成材料的处理。 在引导膜中形成一个开口。 引导膜的上表面是亲水性的，开口的侧表面是疏水性的。 形成固化膜包括施加溶液以覆盖图案形成材料和引导膜，将溶液分离成疏水性嵌段和亲水性嵌段，并固化该溶液。 该溶液含有具有疏水部分和亲水部分的两亲性聚合物。 疏水部分的长度长于亲水部分的长度。 通过从固化膜除去亲水性嵌段形成掩模构件。

公开(公告)号：US08324679B2

公开(公告)日：2012-12-04

申请号：US13430153

申请日：2012-03-26

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US20120241841A1

公开(公告)日：2012-09-27

申请号：US13227882

申请日：2011-09-08

申请人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

发明人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/42352

摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

摘要翻译： 根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱， 设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层， 面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。

公开(公告)号：US08269267B2

公开(公告)日：2012-09-18

申请号：US12904231

申请日：2010-10-14

申请人： Fumitaka Arai ,  Ichiro Mizushima ,  Makoto Mizukami

发明人： Fumitaka Arai ,  Ichiro Mizushima ,  Makoto Mizukami

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42348 ,  H01L29/792

摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.

摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层 膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

公开(公告)号：US20120181602A1

公开(公告)日：2012-07-19

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US08071483B2

公开(公告)日：2011-12-06

申请号：US12564594

申请日：2009-09-22

申请人： Kenichiro Toratani ,  Takashi Nakao ,  Ichiro Mizushima

发明人： Kenichiro Toratani ,  Takashi Nakao ,  Ichiro Mizushima

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： C23C16/0272 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  Y10S438/905

摘要： In a manufacturing process of a semiconductor device by forming a structure film on a substrate in a reaction chamber of a manufacturing apparatus, cleaning inside the reaction chamber is performed. That is, a precoat film made of a silicon nitride film containing boron is deposited on an inner wall of the reaction chamber, a silicon nitride film not containing boron is formed as the structure film on the substrate in the reaction chamber, and the inner wall of the reaction chamber is dry etched to be cleaned. At this time, the dry etching is terminated after boron is detected in a gas exhausted from the reaction chamber.

摘要翻译： 在通过在制造装置的反应室中的基板上形成结构膜的半导体装置的制造工序中，进行反应室内的清洗。 也就是说，在反应室的内壁上沉积由含硼的氮化硅膜制成的预涂膜，在反应室中的基板上形成不含硼的氮化硅膜作为结构膜，内壁 的反应室被干蚀刻以进行清洁。 此时，在从反应室排出的气体中检测到硼后，干法蚀刻终止。

公开(公告)号：US07986013B2

公开(公告)日：2011-07-26

申请号：US12271102

申请日：2008-11-14

申请人： Hiroshi Itokawa ,  Ichiro Mizushima

发明人： Hiroshi Itokawa ,  Ichiro Mizushima

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor device includes a first semiconductor region having a channel region, and containing silicon as a main component, second semiconductor regions sandwiching the first semiconductor region, formed of SiGe, and applying stress to the first semiconductor region, cap layers provided on the second semiconductor regions, and formed of silicon containing carbon or SiGe containing carbon, and silicide layers provided on the cap layers, and formed of nickel silicide or nickel-platinum alloy silicide.

摘要翻译： 半导体器件包括具有沟道区域并且以硅为主要成分的第一半导体区域，夹置由SiGe形成的第一半导体区域的第二半导体区域，并向第一半导体区域施加应力，设置在第二半导体层上的盖层 区域，并且由含硅的碳或含SiGe的碳形成，以及设置在盖层上的由硅化镍或镍 - 铂合金硅化物形成的硅化物层。

公开(公告)号：US07888730B2

公开(公告)日：2011-02-15

申请号：US11687758

申请日：2007-03-19

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

公开(公告)号：US07863166B2

公开(公告)日：2011-01-04

申请号：US12646563

申请日：2009-12-23

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。