公开(公告)号：US20240087953A1

公开(公告)日：2024-03-14

申请号：US18518081

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US20230369130A1

公开(公告)日：2023-11-16

申请号：US18360478

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yip Loh ,  Yan-Ming Tsai ,  Hung-Hsu Chen ,  Chih-Wei Chang ,  Sheng-Hsuan Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092 ,  H01L29/45 ,  H01L21/285

CPC classification number: H01L21/823814 ,  H01L29/665 ,  H01L29/0847 ,  H01L27/0924 ,  H01L29/45 ,  H01L21/28518 ,  H01L21/823828 ,  H01L21/3065

Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.

公开(公告)号：US11411094B2

公开(公告)日：2022-08-09

申请号：US16740881

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US20240136227A1

公开(公告)日：2024-04-25

申请号：US18402859

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Chen ,  Sheng-Hsuan Lin ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/02123 ,  H01L21/02269 ,  H01L21/02274 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

公开(公告)号：US11901229B2

公开(公告)日：2024-02-13

申请号：US17664495

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Chen ,  Sheng-Hsuan Lin ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/76897 ,  H01L21/02123 ,  H01L21/02269 ,  H01L21/02274 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

公开(公告)号：US11854874B2

公开(公告)日：2023-12-26

申请号：US17086754

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522

CPC classification number: H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US20220293474A1

公开(公告)日：2022-09-15

申请号：US17827355

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yip Loh ,  Yan-Ming Tsai ,  Hung-Hsu Chen ,  Chih-Wei Chang ,  Sheng-Hsuan Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092 ,  H01L29/45 ,  H01L21/285

Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.

公开(公告)号：US10964590B2

公开(公告)日：2021-03-30

申请号：US15967056

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei Chou ,  Ken-Yu Chang ,  Sheng-Hsuan Lin ,  Yueh-Ching Pai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/52 ,  H01L29/40

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20210050254A1

公开(公告)日：2021-02-18

申请号：US17086754

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US10535748B2

公开(公告)日：2020-01-14

申请号：US15909838

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.