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1.发明申请AQUEOUS CLEANING TECHNIQUES AND COMPOSITIONS FOR USE IN SEMICONDUCTOR DEVICE MANUFACTURE 有权用于半导体器件制造的清洁清洁技术和组合物公开(公告)号：US20150108578A1
公开(公告)日：2015-04-23
申请号：US14578746
申请日：2014-12-22
发明人： Chun-Li Chou , Shao-Yen Ku , Pei-Hung Chen , Jui-Ping Chuang
IPC分类号： H01L27/088 , H01L29/78 , H01L27/092 , H01L29/06
CPC分类号： H01L27/088 , C11D7/3209 , C11D7/3281 , C11D7/34 , C11D11/0047 , H01L21/02063 , H01L21/823814 , H01L21/823828 , H01L27/092 , H01L29/0653 , H01L29/165 , H01L29/66583 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7842 , H01L29/7848
摘要： Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. Other embodiments related to a semiconductor device resulting from the method.
摘要翻译： 一些实施例涉及半导体器件的制造方法。 在该方法中，提供了包括其上的金属栅电极的半导体工件。 在半导体工件中形成开口以暴露金属栅极的表面。 开口的形成在工件上留下聚合物残留物。 为了从工件中除去聚合物残渣，使用包含有机碱组分的清洁溶液。 与由该方法产生的半导体器件相关的其它实施例。
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公开(公告)号：US11003091B2
公开(公告)日：2021-05-11
申请号：US16740256
申请日：2020-01-10
发明人： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
摘要： A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
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公开(公告)号：US09733568B2
公开(公告)日：2017-08-15
申请号：US14189169
申请日：2014-02-25
发明人： Yi-Rem Chen , Ming-Shane Lu , Chung-Hao Chang , Jui-Ping Chuang , Li-Kong Turn , Fei-Gwo Tsai
CPC分类号： G03F7/3021 , H01L21/67051 , H01L21/6715
摘要： A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer.
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公开(公告)号：US09553090B2
公开(公告)日：2017-01-24
申请号：US14725555
申请日：2015-05-29
IPC分类号： H01L21/70 , H01L27/092 , H01L29/66 , H01L29/423 , H01L29/06 , H01L21/8238
CPC分类号： H01L29/66795 , H01L21/31111 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
摘要翻译： 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的鳍结构。 半导体器件结构还包括覆盖鳍结构的一部分的栅极堆叠，并且栅极堆叠包括功函数层和在功函数层上的金属填充。 半导体器件结构还包括在半导体衬底上并且邻近栅堆叠的隔离元件。 隔离元件与功函数层和金属填充物直接接触。
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公开(公告)号：US11940737B2
公开(公告)日：2024-03-26
申请号：US17315087
申请日：2021-05-07
发明人： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
CPC分类号： G03F7/70433 , G03F1/50 , G03F1/68 , G03F1/70 , G03F1/78 , G03F7/20 , G03F7/70141 , G03F7/70158 , G03F7/70716 , H01L22/30
摘要： A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
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公开(公告)号：US20230275142A1
公开(公告)日：2023-08-31
申请号：US18313190
申请日：2023-05-05
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/49 , H01L29/51 , H01L21/311 , H01L21/762
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/66545 , H01L29/66553 , H01L21/823821 , H01L21/823842 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/42372 , H01L21/823814 , H01L21/823857 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4966 , H01L29/517 , H01L29/7848 , H01L29/7851 , H01L21/31111 , H01L21/76224
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
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公开(公告)号：US20200312985A1
公开(公告)日：2020-10-01
申请号：US16902190
申请日：2020-06-15
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/49 , H01L29/51 , H01L21/311 , H01L21/762
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
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公开(公告)号：US10534272B2
公开(公告)日：2020-01-14
申请号：US16127017
申请日：2018-09-10
发明人： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
摘要： A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
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公开(公告)号：US09559205B2
公开(公告)日：2017-01-31
申请号：US14725118
申请日：2015-05-29
CPC分类号： H01L29/66795 , H01L21/31111 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
摘要翻译： 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的翅片结构和覆盖翅片结构的一部分的栅极堆叠。 栅堆叠包括功函数层和栅介质层。 半导体器件结构还包括位于半导体衬底上并与栅堆叠相邻的隔离元件。 隔离元件与功函数层和栅极电介质层直接接触，并且隔离元件的较低宽度大于隔离元件的上部宽度。
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公开(公告)号：US11682716B2
公开(公告)日：2023-06-20
申请号：US16902190
申请日：2020-06-15
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/49 , H01L29/51 , H01L21/311 , H01L21/762
CPC分类号： H01L29/66795 , H01L21/31111 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/1608 , H01L29/24 , H01L29/267 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/785 , H01L29/7848 , H01L29/7851
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
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