公开(公告)号：US09865736B2

公开(公告)日：2018-01-09

申请号：US15292144

申请日：2016-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chong-Kwang Chang ,  Young-Mook Oh ,  Hak-Yoon Ahn ,  Jung-Gun You ,  Gi-Gwan Park ,  Baik-Min Sung

IPC: H01L29/78 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.

公开(公告)号：US11120998B2

公开(公告)日：2021-09-14

申请号：US16127443

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun Lee ,  Jeon-Il Lee ,  Sung-Woo Kang ,  Hong-Sik Shin ,  Young-Mook Oh ,  Seung-Min Lee

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/51

Abstract: An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.

公开(公告)号：US09985025B1

公开(公告)日：2018-05-29

申请号：US15496145

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Seung-Jin Mun ,  Kwang-Yong Yang ,  Young-Mook Oh ,  Ah-Young Cheon ,  Seung-Mo Ha

IPC: H01L29/00 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/775

Abstract: An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.

公开(公告)号：US20140103405A1

公开(公告)日：2014-04-17

申请号：US13948696

申请日：2013-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chong-Kwang Chang ,  Hak-Yoon Ahn ,  Young-Mook Oh ,  Jung-Hoon Lee ,  Seung-Ho Chae

IPC: H01L29/78 ,  H01L21/302 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/302 ,  H01L29/66477 ,  H01L29/66575

Abstract: A method is provided for fabricating a semiconductor device that includes: forming a gate pattern on a substrate; forming a source/drain in the vicinity of the gate pattern; forming an etch stop film, which covers the gate pattern and the source/drain, on the substrate; forming an interlayer insulating film on the etch stop film; forming a shared contact hole that exposes the gate pattern and the source/drain by etching the interlayer insulating film, wherein a polymer is generated in the shared contact hole a process of etching the interlayer insulating film; removing the polymer by performing etching using hydrogen gas, nitrogen gas or a mixture of hydrogen and nitrogen before etching the etch stop film; and etching the etch stop film.

Abstract translation: 提供一种用于制造半导体器件的方法，该半导体器件包括：在衬底上形成栅极图案; 在栅极图案附近形成源极/漏极; 在衬底上形成覆盖栅极图案和源极/漏极的蚀刻停止膜; 在蚀刻停止膜上形成层间绝缘膜; 通过蚀刻层间绝缘膜形成暴露栅极图案和源极/漏极的共用接触孔，其中在共用接触孔中产生聚合物，蚀刻层间绝缘膜的工艺; 在蚀刻蚀刻停止膜之前通过使用氢气，氮气或氢和氮的混合物进行蚀刻来去除聚合物; 并蚀刻蚀刻停止膜。

公开(公告)号：US10991620B2

公开(公告)日：2021-04-27

申请号：US16282441

申请日：2019-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Lee ,  Sung-Woo Kang ,  Keun-Hee Bai ,  Hak-Yoon Ahn ,  Seong-Han Oh ,  Young-Mook Oh

IPC: H01L21/768 ,  H01L27/11 ,  H01L27/088 ,  H01L23/535 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device includes gates extending in a first direction on a substrate, each gate of the gates including a gate insulation layer, a gate electrode, and a first spacer, first contact plugs contacting the substrate between adjacent ones of the gates, the first contact plugs being spaced apart from sidewalls of corresponding ones of the gates, a second contact plug contacting an upper surface of a corresponding gate electrode, the second contact plug being between first contact plugs, and an insulation spacer in a gap between the second contact plug and an adjacent first contact plug, the insulation spacer contacting sidewalls of the second contact plug and the adjacent first contact plug, and upper surfaces of the second contact plug and the adjacent first contact plug being substantially coplanar with each other.

公开(公告)号：US10050114B2

公开(公告)日：2018-08-14

申请号：US15652396

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bok-Young Lee ,  Sung-Woo Kang ,  Sang-Hyun Lee ,  Hak-Yoon Ahn ,  Young-Mook Oh ,  In-Keun Lee ,  Seong-Han Oh ,  Young-Hun Choi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein, gate structures crossing the fin between the source/drain regions, each including a gate electrode, a first contact structure in electrical contact with a first source/drain region, the first contact structure including a first lower contact and a first upper contact directly thereon, a second contact structure in electrical contact with a gate electrode of a gate structure, the second contact structure including a second lower contact and a second upper contact directly thereon, and a third contact structure in electrical contact with a gate electrode of a second gate structure and in electrical contact with a second source drain region, the third contact structure including a third lower contact and a third upper contact directly thereon.

公开(公告)号：US09786764B2

公开(公告)日：2017-10-10

申请号：US14920267

申请日：2015-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Jin Park ,  Chung-Hwan Shin ,  Sung-Woo Kang ,  Young-Mook Oh ,  Sun-Jung Lee ,  Jeong-Nam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/66545 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/66795 ,  H01L29/7855 ,  H01L2029/7858 ,  H01L2221/1063

Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.