公开(公告)号：US10276570B2

公开(公告)日：2019-04-30

申请号：US15944956

申请日：2018-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Hyung-Jong Lee ,  Sung-Min Kim ,  Chong-Kwang Chang

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/485 ,  H01L23/532 ,  H01L23/528

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

公开(公告)号：US09941281B2

公开(公告)日：2018-04-10

申请号：US15409033

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Hyung-Jong Lee ,  Sung-Min Kim ,  Chong-Kwang Chang

IPC: H01L27/088 ,  H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L23/485 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

公开(公告)号：US20140103405A1

公开(公告)日：2014-04-17

申请号：US13948696

申请日：2013-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chong-Kwang Chang ,  Hak-Yoon Ahn ,  Young-Mook Oh ,  Jung-Hoon Lee ,  Seung-Ho Chae

IPC: H01L29/78 ,  H01L21/302 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/302 ,  H01L29/66477 ,  H01L29/66575

Abstract: A method is provided for fabricating a semiconductor device that includes: forming a gate pattern on a substrate; forming a source/drain in the vicinity of the gate pattern; forming an etch stop film, which covers the gate pattern and the source/drain, on the substrate; forming an interlayer insulating film on the etch stop film; forming a shared contact hole that exposes the gate pattern and the source/drain by etching the interlayer insulating film, wherein a polymer is generated in the shared contact hole a process of etching the interlayer insulating film; removing the polymer by performing etching using hydrogen gas, nitrogen gas or a mixture of hydrogen and nitrogen before etching the etch stop film; and etching the etch stop film.

Abstract translation: 提供一种用于制造半导体器件的方法，该半导体器件包括：在衬底上形成栅极图案; 在栅极图案附近形成源极/漏极; 在衬底上形成覆盖栅极图案和源极/漏极的蚀刻停止膜; 在蚀刻停止膜上形成层间绝缘膜; 通过蚀刻层间绝缘膜形成暴露栅极图案和源极/漏极的共用接触孔，其中在共用接触孔中产生聚合物，蚀刻层间绝缘膜的工艺; 在蚀刻蚀刻停止膜之前通过使用氢气，氮气或氢和氮的混合物进行蚀刻来去除聚合物; 并蚀刻蚀刻停止膜。

公开(公告)号：US09865736B2

公开(公告)日：2018-01-09

申请号：US15292144

申请日：2016-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chong-Kwang Chang ,  Young-Mook Oh ,  Hak-Yoon Ahn ,  Jung-Gun You ,  Gi-Gwan Park ,  Baik-Min Sung

IPC: H01L29/78 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.

公开(公告)号：US10224204B1

公开(公告)日：2019-03-05

申请号：US15891391

申请日：2018-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon Khang ,  Dong-Woo Kang ,  Moon-Han Park ,  Ji-Ho Yoo ,  Chong-Kwang Chang

IPC: H01L21/266 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/768

Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.

公开(公告)号：US09553089B2

公开(公告)日：2017-01-24

申请号：US14995457

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Hyung-Jong Lee ,  Sung-Min Kim ,  Chong-Kwang Chang

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L23/485 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

Abstract translation: 一种半导体器件，包括由第一沟槽分隔的第一和第二鳍状图案; 与第一和第二鳍状图案相交的栅电极; 以及在所述栅极电极的至少一侧上的触点，所述触点接触所述第一鳍状图案，所述触点具有不接触所述第二鳍状图案的底表面，从所述第一沟槽的底部到最顶端的高度 在第一鳍状物的第一鳍状物与第一鳍状物的第一高度相交的区域中的第一鳍状图案和从第一沟槽的底部到第二鳍状图案的最上端的高度， 沿着栅极延伸的方向延伸的接触部将第二翅片图案与第二高度相交，第一高度小于第二高度。