公开(公告)号：US11862571B2

公开(公告)日：2024-01-02

申请号：US17693545

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Gug Min ,  Younhee Kang ,  Min-Woo Song

IPC: H01L23/552 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package including a first semiconductor chip having an upper surface, a lower surface that is opposite to the upper surface, and a sidewall between the upper surface and the lower surface; a capping insulation layer covering the upper surface and the sidewall of the first semiconductor chip; and a shielding layer on the capping insulation layer, wherein a lower portion of the capping insulation layer includes a laterally protruding capping protrusion contacting a lower surface of the shielding layer.

公开(公告)号：US11011473B2

公开(公告)日：2021-05-18

申请号：US16519788

申请日：2019-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younhee Kang ,  Byoung-Gug Min ,  Shi-Kyung Kim ,  Min-Woo Song ,  Jae-Seon Hwang

IPC: H01L23/29 ,  H01L21/00 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.

公开(公告)号：US20140273392A1

公开(公告)日：2014-09-18

申请号：US14290700

申请日：2014-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weon-Hong Kim ,  Min-Woo Song ,  Jung-Min Park

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65

Abstract: A semiconductor integrated circuit device includes a lower electrode formed on a substrate, a first dielectric layer formed of a metal nitride layer, a metal oxynitride layer, or a combination thereof, on the lower electrode, a second dielectric layer formed on the first dielectric layer that includes a zirconium oxide layer, and an upper electrode formed on the second dielectric layer.

Abstract translation: 一种半导体集成电路器件，包括在下电极上形成的下电极，由金属氮化物层形成的第一电介质层，金属氮氧化物层或其组合，形成在第一介电层上的第二电介质层 其包括氧化锆层和形成在第二介电层上的上电极。

公开(公告)号：US11177364B2

公开(公告)日：2021-11-16

申请号：US16938495

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Hoon Lee ,  Hoon-Joo Na ,  Sung-In Suh ,  Min-Woo Song ,  Chan-Hyeong Lee ,  Hu-Yong Lee ,  Sang-Jin Hyun

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66

Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.

公开(公告)号：US10756195B2

公开(公告)日：2020-08-25

申请号：US16179250

申请日：2018-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Hoon Lee ,  Hoon-Joo Na ,  Sung-In Suh ,  Min-Woo Song ,  Chan-Hyeong Lee ,  Hu-Yong Lee ,  Sang-Jin Hyun

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/30 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/66

Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.

公开(公告)号：US20150162201A1

公开(公告)日：2015-06-11

申请号：US14477273

申请日：2014-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Hee Lee ,  Min-Woo Song ,  Seok-Jun Won ,  Hyung-Suk Jung

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/28247 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate electrode and a gate mask sequentially stacked on a substrate is formed. A spacer is formed on a sidewall of the dummy gate structure. The gate mask is formed to expose the dummy gate electrode and to form a recess on the spacer. A capping layer pattern is formed to fill the recess in the spacer. The exposed dummy gate electrode is replaced with a gate electrode.

Abstract translation: 在制造半导体器件的方法中，形成包括依次层叠在基板上的伪栅极电极和栅极掩模的虚拟栅极结构。 在虚拟栅极结构的侧壁上形成间隔物。 形成栅极掩模以暴露伪栅电极并在间隔物上形成凹陷。 形成覆盖层图案以填充间隔件中的凹部。 暴露的虚拟栅电极被栅电极代替。

公开(公告)号：US08796087B2

公开(公告)日：2014-08-05

申请号：US13923470

申请日：2013-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weon-Hong Kim ,  Min-Woo Song ,  Jung-Min Park

IPC: H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3142 ,  H01L21/31604 ,  H01L21/31641 ,  H01L27/10852 ,  H01L28/40

Abstract: A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.

Abstract translation: 一种包括衬底的半导体器件; 基底上的底电极; 所述第一电介质层包括包含Hf，Al，Zr，La，Ba，Sr，Ti和Pb中的至少一种的第一金属氧化物; 在所述第一电介质层上的第二电介质层，所述第二电介质层包括包含Hf，Al，Zr，La，Ba，Sr，Ti和Pb中的至少一种的第二金属氧化物，其中所述第一金属氧化物和所述第二金属 氧化物是不同的材料; 第二电介质层上的第三电介质层，第三电介质层包括金属碳氮氧化物; 以及第三电介质层上的上电极。

公开(公告)号：US11231763B2

公开(公告)日：2022-01-25

申请号：US16466089

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Lee ,  Kwang-Eun Go ,  Kang-Sik Kim ,  Dong-Sub Kim ,  Young-San Kim ,  Won-Min Kim ,  Young-Hyun Ban ,  Min-Woo Song ,  Chung-Hyo Jung

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3234

Abstract: Various embodiments of the present invention relate to an electronic device and a method for controlling heat generated on the surface of the electronic device. The electronic device may comprise a display and a processor, wherein the processor: displays, on the display, graphic elements at the request of a first application; during a first period of time, acquires first information corresponding to the graphic performance of the displayed graphic elements, and identifies a clock control level for controlling operation performance according to execution of the first application; and during a second period of time following the first period of time, identifies a clock value corresponding to the identified clock control level on the basis of the acquired first information, and controls the operation performance according to execution of the first application by using the identified clock value.

公开(公告)号：US10225642B2

公开(公告)日：2019-03-05

申请号：US15328230

申请日：2014-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Woo Song

IPC: H04R1/10

Abstract: An earset, according to various examples, comprises: an electronic device connection unit having a microphone terminal connected to a microphone of the earset, an audio ground terminal connected to an audio ground of the earset, a right speaker terminal, and a left speaker terminal; and a switch for allowing, according to a voltage of the microphone terminal, a right speaker and a left speaker of the earset to be mutually connected with one of the right speaker terminal and the left speaker terminal, and the other one of the right speaker terminal and the left speaker terminal to be connected with a shield ground of the earset. Other examples are possible.

公开(公告)号：US08940611B2

公开(公告)日：2015-01-27

申请号：US14290700

申请日：2014-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weon-Hong Kim ,  Min-Woo Song ,  Jung-Min Park

IPC: H01L29/72 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65

Abstract: A semiconductor integrated circuit device includes a lower electrode formed on a substrate, a first dielectric layer formed of a metal nitride layer, a metal oxynitride layer, or a combination thereof, on the lower electrode, a second dielectric layer formed on the first dielectric layer that includes a zirconium oxide layer, and an upper electrode formed on the second dielectric layer.

Abstract translation: 一种半导体集成电路器件，包括在下电极上形成的下电极，由金属氮化物层形成的第一电介质层，金属氮氧化物层或其组合，形成在第一介电层上的第二电介质层 其包括氧化锆层和形成在第二介电层上的上电极。