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公开(公告)号:US11476220B2
公开(公告)日:2022-10-18
申请号:US17146550
申请日:2021-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jimin Choi , Jung-Hoon Han , Yeonjin Lee , Jong-Min Lee , Jihoon Chang
IPC: H01L25/065 , H01L23/00 , H01L25/18 , H01L21/66
Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.
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公开(公告)号:US10211282B2
公开(公告)日:2019-02-19
申请号:US15712365
申请日:2017-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jong-Min Lee , Jongryul Jun , Eun A Kim , Jung-Bum Lim
IPC: H01L27/108 , H01L49/02 , H01L27/08
Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
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公开(公告)号:US10050129B2
公开(公告)日:2018-08-14
申请号:US15437563
申请日:2017-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Bum Lim , Jong-Ryul Jun , Eun-A Kim , Jong-Min Lee
IPC: H01L21/336 , H01L29/66 , H01L21/768 , H01L21/306 , H01L21/027
Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.
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公开(公告)号:US12288734B2
公开(公告)日:2025-04-29
申请号:US17714202
申请日:2022-04-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Juik Lee , Jong-Min Lee , Jimin Choi , Yeonjin Lee , Jeon Il Lee
IPC: H01L21/00 , H01L23/00 , H01L23/48 , H01L23/522 , H01L23/528 , H01L25/065 , H01L25/10
Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.
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公开(公告)号:US11594595B2
公开(公告)日:2023-02-28
申请号:US17156773
申请日:2021-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong-Min Lee , Hyongsoo Kim , Jongryul Jun
IPC: H01L27/108 , H01L49/02
Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.
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公开(公告)号:US11231763B2
公开(公告)日:2022-01-25
申请号:US16466089
申请日:2017-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong-Min Lee , Kwang-Eun Go , Kang-Sik Kim , Dong-Sub Kim , Young-San Kim , Won-Min Kim , Young-Hyun Ban , Min-Woo Song , Chung-Hyo Jung
IPC: G06F1/08 , G06F1/20 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3234
Abstract: Various embodiments of the present invention relate to an electronic device and a method for controlling heat generated on the surface of the electronic device. The electronic device may comprise a display and a processor, wherein the processor: displays, on the display, graphic elements at the request of a first application; during a first period of time, acquires first information corresponding to the graphic performance of the displayed graphic elements, and identifies a clock control level for controlling operation performance according to execution of the first application; and during a second period of time following the first period of time, identifies a clock value corresponding to the identified clock control level on the basis of the acquired first information, and controls the operation performance according to execution of the first application by using the identified clock value.
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公开(公告)号:US10903310B2
公开(公告)日:2021-01-26
申请号:US16787426
申请日:2020-02-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong-Min Lee , Hyongsoo Kim , Jongryul Jun
IPC: H01L49/02 , H01L27/108
Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.
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公开(公告)号:US20180211968A1
公开(公告)日:2018-07-26
申请号:US15923408
申请日:2018-03-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
IPC: H01L27/11565 , H01L27/11582 , H01L21/768 , H01L23/528 , H01L27/11575 , H01L27/11573 , H01L23/544 , H01L27/1157 , H01L23/522
CPC classification number: H01L27/11565 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/544 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2223/5442 , H01L2223/54433 , H01L2223/54453
Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.
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公开(公告)号:US20230014037A1
公开(公告)日:2023-01-19
申请号:US17690154
申请日:2022-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Euntaek Jung , Jaeho Kim , Joonsung Kim , Jiwon Kim , Sukkang Sung , Sangdon Lee , Jong-Min Lee
IPC: H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L23/528 , G11C16/04
Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.
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公开(公告)号:USRE48482E1
公开(公告)日:2021-03-23
申请号:US16804630
申请日:2020-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
IPC: H01L27/11565 , H01L27/11582 , H01L21/768 , H01L27/1157 , H01L23/528 , H01L23/522 , H01L27/11575 , H01L27/11573 , H01L23/544
Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.
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