公开(公告)号：US12159859B2

公开(公告)日：2024-12-03

申请号：US17696989

申请日：2022-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin Choi ,  Jeonil Lee ,  Jongmin Lee ,  Juik Lee

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

公开(公告)号：US12072374B2

公开(公告)日：2024-08-27

申请号：US17540745

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Yeonjin Lee ,  Minjung Choi ,  Jimin Choi

IPC: G01R31/28 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: G01R31/2884 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05097 ,  H01L2224/06515

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

公开(公告)号：US11646225B2

公开(公告)日：2023-05-09

申请号：US17039431

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L27/10 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US11881422B2

公开(公告)日：2024-01-23

申请号：US17670907

申请日：2022-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hujong Lee ,  Minsoo Park ,  Jimin Choi ,  Kunjin Ryu ,  Byungkook Yoo ,  Seungjun Lee ,  Mingu Chang ,  Younboo Jung

IPC: H01L21/677 ,  A47B57/06 ,  B65G1/04 ,  B65G1/10 ,  B66C19/00

CPC classification number: H01L21/67769 ,  A47B57/06 ,  B65G1/0464 ,  B65G1/10 ,  B66C19/00

Abstract: A storage system includes a storage device and a transfer device. The storage device includes a guide bar, a plurality of upper shelves connected to the guide bar, the plurality of upper shelves storing a material to be transferred, a plurality of lower shelves disposed under the plurality of upper shelves, the plurality of lower shelves storing the material, a plurality of guides connected to the plurality of upper shelves, and a shelf returning device connected to a selected upper shelf from among the plurality of upper shelves. The transfer device includes a body, a drive module attached to the body, the drive module moving the transfer device to be adjacent to the storage device, a handling module attached to the body, the handling module handling the material, and a shelf moving module attached to the body or the handling module, the shelf moving module contacting a selected guide from among the plurality of guides.

公开(公告)号：US20230138616A1

公开(公告)日：2023-05-04

申请号：US18051623

申请日：2022-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Jongmin Lee ,  Yeonjin Lee ,  Jeonil Lee ,  Jimin Choi

IPC: H01L21/02 ,  H01L23/14 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device including a semiconductor substrate, a first interlayer insulating layer arranged on the semiconductor substrate, a low dielectric layer arranged on the first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer sequentially arranged on the low dielectric layer, and a through silicon via penetrating the semiconductor substrate and the first interlayer insulating layer, wherein the semiconductor substrate, the first interlayer insulating layer, and the low dielectric layer constitute a chamfered structure including a first chamfered surface parallel to the top surface of the semiconductor substrate and a second chamfered surface inclined with respect to the top surface of the semiconductor substrate and connected to the first chamfered surface may be provided.

公开(公告)号：US20230080862A1

公开(公告)日：2023-03-16

申请号：US17662301

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Jongmin Lee ,  Jimin Choi

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device according to the disclosure includes a substrate, a transistor connected to the substrate, and a wiring structure including contact wirings electrically connected to the transistor. The wiring structure further includes a first wiring insulating layer, a first material layer contacting the first wiring insulating layer, a second material layer contacting the first material layer, and a second wiring insulating layer contacting the second material layer. The first material layer includes SiN, and the second material layer includes SiCN. A dielectric constant of the first wiring insulating layer is greater than a dielectric constant of the second wiring insulating layer.

公开(公告)号：US10211091B2

公开(公告)日：2019-02-19

申请号：US15334469

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/108

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US12288734B2

公开(公告)日：2025-04-29

申请号：US17714202

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juik Lee ,  Jong-Min Lee ,  Jimin Choi ,  Yeonjin Lee ,  Jeon Il Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

公开(公告)号：US12272581B2

公开(公告)日：2025-04-08

申请号：US17493198

申请日：2021-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjune Bae ,  Jimin Choi ,  Hyungsik Um ,  Jeongjae Bang ,  Hyeonhui Cho

IPC: H01L21/677 ,  B61B3/02 ,  B61B12/02 ,  B65G1/04 ,  B66C9/04 ,  F16C35/00

Abstract: A steering device for an OHT according to some example embodiments of the present inventive concepts includes: an LM block; a steering plate fixedly installed to the LM block and provided with an insertion groove; a link installed in the insertion groove of the steering plate and tilted; a main bearing having an outer circumferential surface in contact with the link to reduce friction when the link is tilted; and a guide roller rotatably installed on a protrusion protruding from the link.

公开(公告)号：US12183660B2

公开(公告)日：2024-12-31

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Jongmin Lee ,  Jimin Choi ,  Yeonjin Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.