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    Thermal pad, semiconductor chip including the same and method of manufacturing the semiconductor chip
    1.
    发明授权
    Thermal pad, semiconductor chip including the same and method of manufacturing the semiconductor chip 有权

    公开(公告)号：US12159859B2

    公开(公告)日：2024-12-03

    申请号：US17696989

    申请日：2022-03-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jimin Choi ,  Jeonil Lee ,  Jongmin Lee ,  Juik Lee

    IPC: H01L25/065 ,  H01L23/367 ,  H01L23/42 ,  H01L23/48

    Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

    Antenna structure and electronic device including the same
    2.
    发明授权
    Antenna structure and electronic device including the same 有权

    公开(公告)号：US12107334B2

    公开(公告)日：2024-10-01

    申请号：US18075850

    申请日：2022-12-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bumhee Lee ,  Seungtae Ko ,  Junsig Kum ,  Yoongeon Kim ,  Seokmin Lee ,  Youngju Lee ,  Jongmin Lee ,  Seungho Choi

    IPC: H01Q1/24 ,  H01Q21/00

    CPC classification number: H01Q21/0006 ,  H01Q1/246

    Abstract: The disclosure relates to a fifth generation (5G) or pre-5G communication system supporting higher data rates after a fourth generation (4G) communication system such as Long Term Evolution (LTE). A module in a wireless communication system is provided. The module includes a plurality of antenna elements, an antenna substrate coupled to the plurality of antenna elements, a metal plate coupled to the antenna substrate, a calibration substrate coupled to a Radio Frequency (RF) component on a first face, and a conductive adhesive material for electrical coupling between the metal plate and the calibration substrate. The conductive adhesive material may be coupled to the calibration substrate on a second face different from the first face of the calibration substrate. The conductive adhesive material may include an air gap formed along a signal line included in the calibration substrate.

    Semiconductor devices including line identifier
    3.
    发明授权
    Semiconductor devices including line identifier 有权

    公开(公告)号：US12080645B2

    公开(公告)日：2024-09-03

    申请号：US18114337

    申请日：2023-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yewon Shin ,  Jaesun Yun ,  Seungjun Lee ,  Jongmin Lee

    IPC: H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group.

    MEMORY CONTROLLERS, MEMORY SYSTEMS, AND MEMORY MODULES
    4.
    发明公开
    MEMORY CONTROLLERS, MEMORY SYSTEMS, AND MEMORY MODULES 审中-公开

    公开(公告)号：US20230147227A1

    公开(公告)日：2023-05-11

    申请号：US17814964

    申请日：2022-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

    IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15 ,  G06F17/16

    CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/076 ,  H03M13/1575 ,  G06F17/16

    Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

    SEMICONDUCTOR DEVICE WITH CRACK-PREVENTING STRUCTURE
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH CRACK-PREVENTING STRUCTURE 有权

    公开(公告)号：US20250157948A1

    公开(公告)日：2025-05-15

    申请号：US19023084

    申请日：2025-01-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

    IPC: H01L23/00 ,  H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

    Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

    Semiconductor device with crack-preventing structure
    8.
    发明授权
    Semiconductor device with crack-preventing structure 有权

    公开(公告)号：US12230587B2

    公开(公告)日：2025-02-18

    申请号：US17706013

    申请日：2022-03-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

    IPC: H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

    Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12089396B2

    公开(公告)日：2024-09-10

    申请号：US17724344

    申请日：2022-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin Lee

    IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

    CPC classification number: H10B12/315 ,  H01L28/92 ,  H10B12/50 ,  H10B12/0335 ,  H10B12/09

    Abstract: A semiconductor device may include a cell capacitor including first lower electrodes, a first upper support layer pattern, a first dielectric layer, and a first upper electrode. The decoupling capacitor may include second lower electrodes, a second upper support layer pattern, a second dielectric layer, and a second upper electrode. The first and second lower electrodes may be arranged in a honeycomb pattern at each vertex of a hexagon and a center of the hexagon. The first upper support layer pattern may be connected to upper sidewalls of the first lower electrodes. The first upper support layer pattern may correspond to a first plate defining first openings. The second upper support layer pattern may be connected to upper sidewalls of the second electrodes. The second upper support layer pattern may correspond to a second plate defining second openings having a shape different from a shape of the first opening.

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